The cdb42l73 system overview, 1 power supply circuitry, 2 digital inputs and outputs – Cirrus Logic CDB42L73 User Manual
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CDB42L73
2. THE CDB42L73 SYSTEM OVERVIEW
The CDB42L73 evaluation board is a convenient platform for evaluating the CS42L73 ultralow-power mobile and
telephony CODEC. It supports multiple power supply and signal I/O configurations, including the option to drive the
CS42L73 externally (which bypasses on-board circuitry). The CDB42L73 is also a good component and layout ref-
erence for the CS42L73.
through
below describe the various features of the CDB42L73 evaluation board in detail.
lists several useful performance measurement tips when evaluating the CDB42L73.
2.1
Power Supply Circuitry
The CDB42L73 is designed to be powered by a single +5 V DC power supply. This can be provided by an
external +5 V power supply unit or a regular USB connection, selectable via jumper pin block J50. If using
a USB connection to supply power, the VP supply pin of the CS42L73 requires an external source (J7 or
J49); this is due to the high power requirements of driving a speakerphone. At full speakerphone volume,
the current consumption of the VP supply pin may exceed the current supply capabilities of a typical USB
connection.
Low-dropout regulators (LDOs) step down the +5 V supply to provide clean and stable 3.3 V and 1.8 V rails
to all the onboard circuitry and the CS42L73.
There is also a switching buck regulator which may be used to supply a 1.8 V rail. The buck regulator’s
source, either the main +5 V supply or an external battery, is selectable via jumper pin block J8. It is en-
abled/disabled with J15. The external battery connection is J49.
Jumper pin blocks J10, J11, J12, J13, and J14 select the power supply source for the CS42L73 supply pins.
In most cases, the selections are between an external supply, the LDO-derived 1.8 V, or the buck-derived
1.8 V.
Jumper pin block J25 selects the source of the CS42L73’s interface voltage, VL. When J25 is shunted in
the “NORM” position, all devices on the board (including the CS42L73) share the same VL supply as se-
lected on J11. However, in strict battery life testing of the CS42L73, it may be useful to decouple the power
usage of VL of peripheral devices (such as signal level shifters) from that of the CS42L73. When J25 is
shunted In the “+1.8V LDO” position, VL for peripheral devices on the CDB42L73 is sourced from the +1.8 V
LDO, while VL for the CS42L73 is determined by the selection on J11.
2.2
Digital Inputs and Outputs
The S/PDIF interface on the CDB42L73 accepts coaxial or optical connections for both inputs and outputs.
S/PDIF inputs are handled by the CS8416 receiver; S/PDIF outputs by the CS8406 transmitter. On the
CDB42L73, the CS8416 is configured to operate only in master mode, while the CS8406 is to work only in
slave mode.
Please note that the S/PDIF interface is routed only to the Audio Serial Port (ASP) of the CS42L73; however,
the ASP may also be driven externally via header J23. The Voice Serial Port (VSP) and Auxiliary Serial Port
(XSP) may only be driven externally via headers J24 and J22, respectively.
A complete description of the CS8416 S/PDIF receiver and CS8406 S/PDIF transmitter can be found in their
respective datasheets, downloadable from
2.3
Digital Mic Input
The digital mic input header, J26, allows up to two digital microphones to interface with the CS42L73. A rib-
bon cable is required to connect the digital microphones to J26.