Cirrus Logic CDB4265 - Manual (Page 13)

CDB4265
DS657DB1 13
5.3 SUBCLOCK SOURCE CONTROL - ADDRESS 03H
5.3.1 SUBCLOCK SOURCE (BITS 1:0)
Default = 01
Function:
This bit selects the source of the CS4265 SCLK and LRCK signals. Table 2 shows the available set-
tings.
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved Reserved SUBCLK1 SUBCLK0
Table 2. CS4265 Subclock Source
SUBCLK1 SUBCLK0 CS4265 Subclock Source
0 0 - CS4265 is Master
- PCM Header Subclocks are Output from CS4265
0 1 Reserved
1 0 - CS4265 is Slave to PCM Header
- PCM Header Subclocks are an Input
1 1 - CS4265 is Slave to CS8416 subclocks
- PCM Header Subclocks are Output from CS8416 Subclocks