Cirrus Logic CS4228A - Manual (Page 17)

CS4228A
17
LRCK
SCLK
Left Channel
Right Channel
6 5 4 3 2 1 0 9 8 7 15 14 13 12 11 10 6 5 4 3 2 1 0 9 8 7 15 14 13 12 11 10 SDINx
Figure 12. Right Justified Serial Audio Formats
Right Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
16 32, 48, 64, 128 Fs
32, 64 Fs BRM, 48 Fs available in slave mode only
HRM
20 48, 64, 128 Fs
64 Fs BRM, 48 Fs available in slave mode only
HRM
24 48, 64, 128 Fs
64 Fs BRM, 48 Fs available in slave mode only
HRM
LRCK
SCLK
SDIN1 LSB MSB
20 clks
64 clks 64 clks
LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB MSB
DAC1 DAC3 DAC5 DAC2 DAC4 DAC6
20 clks 20 clks 20 clks 20 clks 20 clks
20 clks
ADCL ADCR
20 clks
SDOUT
Left Channel Right Channel
Figure 13. One Line Data Serial Audio Format
One Line Data Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
20 128 Fs 6 inputs, 2 outputs, BRM only