GW Instek GDS-2000A series Single sheet for LA Quick start guide User Manual
Page 2
6. Press Event Table to view or save the decoded data
in a list.
7. Press Edit Labels to create an on-screen label for
the bus.
I
2
C Bus
The I2C bus is a 2 wire interface with a serial data line
(SDA) and serial clock line (SCLK). The I2C protocol
supports 7 or 10 bit addressing and multiple masters.
1. Press the Bus soft-key and select I
2
C.
2. Press Define Inputs to select the SCLK and SDA
inputs.
3. Press Thresholds to set the thresholds.
There are 5 pre-set threshold levels in
addition to the User-defined threshold
setting (TTL, 5.0V CMOS, 3.3V CMOS,
2.5V CMOS, ECL, PECL, 0V).
4. Press the Include R/W in Address soft-key to set
whether a read/write bit is included in the
address.
5. Press Bus Display to configure how the data is
displayed, either hex or binary.
6. Press Event Table to view or save the decoded data
in a list.
The Data Detail option allows you to also
view the data at a particular address. This is
only for I
2
C buses.
7. Press Edit Labels to create an on-screen label for
the bus.
SPI Bus
The serial peripheral interface (SPI) is a full duplex 4
wire synchronous serial interface. The word size is
configurable from 4 to 32 bits. The SPI bus triggers on
the data pattern at the start of each framing period.
1. Press the Bus soft-key and select SPI.
2. Press Define Inputs to select the SCLK, SS, MOSI
and MISO inputs.
3. Press Thresholds to set the thresholds.
There are 5 pre-set threshold levels in
addition to the User-defined threshold
setting (TTL, 5.0V CMOS, 3.3V CMOS,
2.5V CMOS, ECL, PECL, 0V).
4. Press Configure to set the data line logic level,
SCLK edge polarity, word size and bit order.
5. Press Bus Display to configure how the data is
displayed, either hex or binary.
6. Press Event Table to view or save the decoded data
in a list.
7. Press Edit Labels to create an on-screen label for
the bus.
Parallel Bus
The digital channels can be configured as a parallel
bus. The number of bits that define the bus as well as
which bit is used as the bus clock can also be
configured.
1. Press the Bus soft-key and select Parallel.
2. Press Define Inputs to select the number of bits to
use in the parallel bus, which digital channels are
set to which bits in the parallel bus and which bit,
if any, is used for a clock signal.
3. Press Thresholds to set the thresholds.
There are 5 pre-set threshold levels in
addition to the User-defined threshold
setting (TTL, 5.0V CMOS, 3.3V CMOS,
2.5V CMOS, ECL, PECL, 0V).
Thresholds can be set for each 4 lots of
digital channels, i.e., D0~D3, D4~D7 and so
on.
4. Press Bus Display to configure how the data is
displayed, either hex or binary.
5. Press Event Table to view or save the decoded data
in a list.
6. Press Edit Labels to create an on-screen label for
the bus.
Trigger Settings
The Logic Analyzer option adds Bus and Logic triggers
to the GDS-2000A.
Note that the digital channels can also be set as the
source for the traditional Edge and Pulse Width
triggers, but will not be covered here as the operation
is covered in the user manual.
Logic Trigger Settings
The digital channels can be set up to trigger on
specified logic levels and for a specified clock edge.
1. Press the trigger
key and select
Type > Others > Logic.
2. Press Define Inputs to set the digital logic to
trigger on.
Only 1 bit can be set as the clock bit.
The digital logic will be reflected in the
Trigger Status icon under the graticule.
3. Press When to configure the triggering conditions
for the logic that was defined in the Define Inputs
menu.
The scope can be configured to trigger when
the defined logic is true or false.
The trigger timing for when the selected
logic is true can also be configured.
4. Press Thresholds to set the thresholds.
There are 5 pre-set threshold levels in
addition to the User-defined threshold
setting (TTL, 5.0V CMOS, 3.3V CMOS,
2.5V CMOS, ECL, PECL, 0V).
Thresholds can be set for each 4 lots of
digital channels, i.e., D0~D3, D4~D7 and so
on.
5. Press Clock Edge to set the transition for the
selected clock edge, if any.
6. Press Mode to select either Auto (untriggered roll)
or Normal triggering modes.
7. Press Holdoff to set the hold off time.
Bus Trigger Settings -UART
The digital channels can be set up to trigger on UART
specific conditions.
1. Configure the Bus key to UART.
The UART option needs to be set in the Bus
menu first before the UART trigger settings
can be configured.
2. Press the trigger
key and select
Type > Others > Bus.
3. Press Trigger On to set triggering conditions.
There are 8 UART triggering conditions: Tx,
Start Bit, Rx Start Bit, Tx End of Packet,, Rx
End of Packet, Tx Data, Rx Data, Tx Parity
Bit, Rx Parity Bit.
4. If Tx Data or Rx Data was selected, press Data to
configure what data to trigger on.
Bus Trigger Settings –I
2
C
The digital channels can be set up to trigger on I
2
C
specific conditions.
1. Configure the Bus key to I
2
C.
The I
2
C option needs to be set in the Bus
menu first before the I
2
C trigger settings can
be configured.
2. Press the trigger
key and select
Type > Others > Bus.
3. Press Trigger On to set triggering conditions.
There are 7 I
2
C triggering conditions: Start,
Repeat Start, Stop, Missing Ack, Address,
Data, Data/Address.
4. If Data or Data/Address was selected as the trigger
condition, press Data to configure what data to
trigger on.
5. If Address or Data/Address was selected as the
trigger condition, press Address to configure the
address and the addressing mode to trigger on.
An address preset can also be chosen if
Address was selected as the trigger condition.
This option is not available for the
Data/Address triggering condition.
Press Direction to configure read/write direction.
6. Press Mode to select either Auto (untriggered roll)
or Normal triggering modes.
S
PECIFICATIONS
Logic Analyzer
Sample Rate
500MSa/s
Bandwidth
200MHz
Record Length
2M max
Input Channels
16 Digital (D15 - D0) or
8 Digital (D7~D0)
Trigger type
Edge, Pattern, Pulse Width,
Serial bus (I2C, SPI, UART)
Thresholds
Quad-D0~D3, D4~D7 . . .
Thresholds
Threshold selections
TTL, CMOS, ECL, PECL, User
Defined
User-defined Threshold
Range
±10V
Maximum Input Voltage
±40V
Minimum Voltage
Swing
±500mV
Vertical Resolution
1 bit