Watlow QPAC Modular SCR Power Control Service - Manual (Page 29)

WATLOW QPAC Service Manual 29 Troubleshooting, Chapter 5
Cards
U12 is used to detect the loss of L2 phase, (phase loss) and U13 is used to detect
the proper phase rotation. U7B, U7C, and U7D combined phase loss, phase rota-
tion, PLL, and the thermostat for ESD.
Scope picture 2 shows the AC input (L1 to L3) at TP1 and TP6 (FWZ) after zero
cross calibration. Scope picture 3 is the high frequency clock TP9 (MCK). Scope
picture 4 shows the sequence of operation at approximately 50% power. From top
to bottom:
1.
FWZ (zero cross reference)
2. Timing output A phase (U8, Pin 12)
3. Timing output B phase (U8, Pin 8)
4. Timing output C phase (U5, Pin 8)
5. Load Current T1
6. Load current T2
7. Load current T3
The output board contains the SCR protection, the output drivers, and power resis-
tors to form the artificial neutral. See schematic 02-0798 on Page 35.
QCD and CA Cards (08-5286 and 08-5285)
FWZ at Pin 3 is shaped by Q1 to form a window around the zero cross point. See
Scope Picture 5. This is summed with the command signal by U1A and with the
ESD line by U1B to provide a high output at Pin 11 if the input signal is high, the
ESD signal is high, and it is at zero cross. The CA card accepts an AC signal and
U2 gives a high for each half cycle. See schematic 02-0672 (QCD) and 02-0673
(QCA) on Page 36 - 37.
QBF Card (08-5289)
Q1 and U2B make up the zero cross notch providing that the ESD signal is high.
Q2, and Q3 make up a linear ramp with a 4 second time base and approximately 2
volts high U1C is the input amplifier with the Bias and Gain amplifiers, and U1D is
used as a comparator to give a high output any time the ramp exceeds the input
signal. U2A adds the output of the comparator and the FWZ signal to give output
pulses only during the zero cross notch. See scope picture 5 (TP1, FWZ), scope
picture 6 (TP2 & 3, ramp top and comparator output bottom, scope picture 7, (TP2
& 4 ramp top and output pulses bottom). See schematic 02-0657 on Page 38.
QBV Card (08-5342)
U2A is used to make up the FWZ signal. U1A is a flip-flop clocked by the FWZ to
provide a square wave of one full cycle duration. U2B provides a delayed pulse,
slightly after the end of each full cycle. The input signal, goes into Q2 (emitter fol-
lower) which produces a collector current proportional to the voltage across the
emitter resistor. Q1 is used as a zener to linearize the output. Q3 is an emitter fol-
lower used to discharge C5 every other half cycle (Q5 prevents C5 from being dis-
charged when ON). Once C5 voltage reaches the program point of Q4 (R14, R16)
it charges C5 through R19 and sets U1B. Since C5 can only reach its peak when
Q5 is OFF, (TP2 low) U1B will always stay on for one full cycle. With U1B output
high, U2D will allow two output pulses insuring one full cycle output minimum. If
ESD is low, U2D is inhibited from allowing FWZ pulses. See Scope Picture 8 for
TP1 & TP2 FWZ top and TP2 bottom, Scope Picture 9 for TP1 FWZ top and count
clear bottom, Scope Picture 10 for TP1 & TP4 FWZ top and output on the bottom,
Scope Picture 11 for TP1, 2, 4, 5 showing FWZ, SQ wave, output and the stair-
case waveform on C5. See schematic 02-0729 on Page 39.