Teledyne LeCroy QPHY-LPDDR2 - Manual (Page 48)

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QPHY-LPDDR2-OM-G Rev B
Figure 27. Slew Rate [JESD209-2D figure 124]
DQS and DQS# signals must be monotonic between VIL(dc)max and VIH(dc)min.
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(dc)max and the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined
as the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc).
tIS(base) - Address and Control Input Setup Time
Input waveform timing is referenced from the input signal crossing at the VIH(ac)min level to the
differential clock crosspoint at VREF for a rising signal, and from the input signal crossing at the
VIL(ac)max level to the differential clock crosspoint at VREF for a falling signal applied to the device
under test. See table below.