Impulse 3405 - Manual (Page 13)

Technical Description
Sealevel Systems VERSA COMM+4/EX Page 10
Technical Description
The VERSA COMM+4/EX utilizes the 16C554 UART. This chip features
programmable baud rate, data format, interrupt control and a 16-byte input and
output FIFO, and is functionally 4 16C550 UARTs. A full array of advanced
UARTs is also available for this card. Contact Sealevel Systems, Inc. for more
information.
Features
• ‘Shareable’ IRQs allow more than one port to share a single IRQ with
appropriate software drivers
• IRQs 3-7, 9-12, 15 supported
• 16C554 buffered Quad UART Standard
• 16 Bit address decode allows for easier integration
• Speeds up to 460.8 K bps
• Multiple clocking modes insuring compatibility with existing software
products
Interrupt Status Port
The VERSA COMM+4/EX provides the user with an Interrupt Status Port
(ISP) for greater throughput when servicing multiple ports on a single interrupt
line. The ISP is a read only 8-bit register that sets a corresponding bit when an
interrupt is pending. Port 1 interrupt line corresponds with Bit D0 of the status
port, Port 2 with D1 etc.
The ISP is located at Base+7 on each port (Example: Base = 280 Hex, Status
Port = 287, 28F… etc.). This allows any one of eight locations to be read to
obtain the value in the status register. All four status ports on the
VERSA COMM+4/EX are identical, so any one of the four can be read to
determine which interrupt is pending. In the following example Channel 2 has an
interrupt pending. D4 through D7 are not driven into the interrupt status register
and can be 1’s or 0’s.
Bit Position: 7 6 5 4 3 2 1 0
Value Read: 0 0 0 0 0 0 1 0