Atec Superior-Electric-L116b - Manual (Page 14)

PCB LAYOUT
Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops. The input and
output capacitors must be directly connected to the input, output, and ground pins of the regulator using traces which do not have
other currents flowing in them (Kelvin connect).
The best way to do this is to lay out C
IN
and C
OUT
near the device with short traces to the V
IN
, V
OUT
, and ground pins. The regulator
ground pin should be connected to the external circuit ground so that the regulator and its capacitors have a "single point ground".
It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane were used at the
ground points of the IC and the input and output capacitors. This was caused by varying ground potentials at these nodes resulting
from current flowing through the ground plane. Using a single point ground technique for the regulator and it’s capacitors fixed the
problem. Since high current flows through the traces going into V
IN
and coming from V
OUT
, Kelvin connect the capacitor leads to
these pins so there is no voltage drop in series with the input and output capacitors.
LLP MOUNTING
The SDE06A (No Pullback) 6-Lead LLP package requires specific mounting techniques which are detailed in National Semicon-
ductor Application Note # 1187. Referring to the section PCB Design Recommendations in AN-1187 (Page 5), it should be noted
that the pad style which should be used with the LLP package is the NSMD (non-solder mask defined) type. Additionally, it is
recommended the PCB terminal pads to be 0.2 mm longer than the package pads to create a solder fillet to improve reliability and
inspection.
The input current is split between two V
IN
pins, 1 and 6. The two V
IN
pins must be connected together to ensure that the device
can meet all specifications at the rated current.
The thermal dissipation of the LLP package is directly related to the printed circuit board construction and the amount of additional
copper area connected to the DAP.
The DAP (exposed pad) on the bottom of the LLP package is connected to the die substrate with a conductive die attach adhesive.
The DAP has no direct electrical (wire) connection to any of the pins. There is a parasitic PN junction between the die substrate
and the device ground. As such, it is strongly recommend that the DAP be connected directly to the ground at device lead 2 (i.e.
GND). Alternately, but not recommended, the DAP may be left floating (i.e. no electrical connection). The DAP must not be con-
nected to any potential other than ground.
For the LP38690SD and LP38692SD in the SDE06A 6-Lead LLP package, the junction-to-case thermal rating,
θ
JC
, is 10.4°C/W,
where the case is the bottom of the package at the center of the DAP. The junction-to-ambient thermal performance for the
LP38690SD and LP38692SD in the SDE06A 6-Lead LLP package, using the JEDEC JESD51 standards is summarized in the
following table:
Board
Type
Thermal
Vias
θ
JC
θ
JA
JEDEC
2–Layer
JESD 51-3
None 10.4°C/W 237°C/W
JEDEC
4–Layer
JESD 51-7
1 10.4°C/W 74°C/W
2 10.4°C/W 60°C/W
4 10.4°C/W 49°C/W
6 10.4°C/W 45°C/W
RFI/EMI SUSCEPTIBILITY
RFI (radio frequency interference) and EMI (electromagnetic interference) can degrade any integrated circuit’s performance be-
cause of the small dimensions of the geometries inside the device. In applications where circuit sources are present which generate
signals with significant high frequency energy content (> 1 MHz), care must be taken to ensure that this does not affect the IC
regulator.
If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes from the output
of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the IC.
If a load is connected to the IC output which switches at high speed (such as a clock), the high-frequency current pulses required
by the load must be supplied by the capacitors on the IC output. Since the bandwidth of the regulator loop is less than 100 kHz,
the control circuitry cannot respond to load changes above that frequency. This means the effective output impedance of the IC at
frequencies above 100 kHz is determined only by the output capacitor(s).
In applications where the load is switching at high speed, the output of the IC may need RF isolation from the load. It is recommended
that some inductance be placed between the output capacitor and the load, and good RF bypass capacitors be placed directly
across the load.
PCB layout is also critical in high noise environments, since RFI/EMI is easily radiated directly into PC traces. Noisy circuitry should
be isolated from "clean" circuits where possible, and grounded through a separate path. At MHz frequencies, ground planes begin
to look inductive and RFI/ EMI can cause ground bounce across the ground plane. In multi-layer PCB applications, care should be
taken in layout so that noisy power and ground planes do not radiate directly into adjacent layers which carry analog power and
ground.
LP38690
LP38692
14 Copyright © 1999-2012, Texas Instruments Incorporated