Atec Agilent-E4421B-24B-32B-33B-35B-36B - Manual (Page 24)

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User equipment (UE) setup
FIR filter
Root Nyquist, Nyquist a=0 to 1
Gaussian BbT= 0 to 1
Chip rate
1 kcps to 4.25 Mcps
Primary scrambling code
0 to 16777215
Secondary scrambling offset
0 to 15
Uplink synchronization signal setup
Timing offset range: Timing offset 512 to 2560 chips
Slot delay 0 to 119 slots
Synchronization signal System Frame Number (SFN) reset
or frame clock
Frame clock interval 10 ms, 20 ms, 40 ms, 80 ms
Frame clock polarity Positive, negative
SFN RST polarity Positive, negative
Sync trigger mode Single, continuous
BBG data clock (chip clock) setup
internal, external
External clock rate: x 1 (3.84 MHz), x 2 (7.68 MHz) x 4 (15.36 MHz)
External clock polarity: Positive, negative
Uplink channel configurations
Pre-set channel type
Reference measurement channel: 12.2 kbps, 64 kbps, 144 kbps,
384 kbps (3GPP Std 25.141 v3.2)
UDI 64 k (ISG typical radio parameter sets, version 1.2)
AMR 12.2 k (ISG typical radio parameter sets, version 1.2)
User defined channels
One DPCCH, one DPDCH, up to 6 transport channels
DPCCH (Dedicated Physical Control Channel)
Power -40 to 0 dB
Beta 0 to 15 (coupled to power)
Channel code 0 to 255
TFCI pattern PN9, PN15, 0 to 03FF hex, user file
TFCI state (Depends on slot format)
Symbol rate 15 ksps (Non adjustable)
FBI pattern PN9, PN15, 0 to 3FFFFFFF hex, user file
FBI state (Depends on slot format)
Slot format 0 to 5
Interleaver On (non adjustable)
TPC pattern PN9, PN15, 4-bit repeating pattern,
user file, up/down, down/up, all up,
all down
TPC pattern steps 1 to 80
DPDCH (Dedicated Physical Data Channel)
Power Off, -40 to 0 dB
Beta 0 to 15 (coupled to power)
Channel code 0 to 255 (maximum value depends
on symbol rate/slot format)
Data PN9, PN15, 4-bit repeating pattern,
user file, transport channel
Symbol rate 15, 30, 60, 120, 240, 480, 960 ksps
depending on slot format
Slot format 0 to 6
Transport channel setup
Block size 0 to 5000
Number of blocks 0 to 4095
Coding 1/2 convolutional, 1/3 convolutional,
turbo, none
TTI 10 ms, 20 ms, 40 ms, and 80 mSec
Data PN9, 4-bit repeating pattern, user file
Rate matching attributes 1 to 256
CRC size 0, 8, 12, 16, 24
Error insertion BLER or BER, or none
BLER (Block Error Rate) 0 to 1 (resolution 0.001)
BER (Bit Error Rate) 0 to 1 (resolution 0.0001)
Bits frame Automatically calculated
Input
Synchronization signal (SFN RST or frame clock): Pattern trigger
in BBG data clock (chip clock): data clock in
Output
Chip clock out (3.84 MHz): Data clock out
Frame timing out: system sync out
DPDCH (I) symbol data: event1 out
DPDCH (I) symbol clock: event2 out
DPCCH (Q) symbol data: data out