Diodes ZXGD3103N8 User Manual
Page 10
ZXGD3103N8
ZXGD3103N8
Document number: DS32255 Rev. 2 - 2
10 of 12
November 2011
© Diodes Incorporated
A Product Line of
Diodes Incorporated
Design considerations
It is advisable to decouple the ZXGD3103 closely to V
CC
and ground due to the possibility of high peak gate
currents with a 1
μF X7R type ceramic capacitor as shown in Figure 2. The Gate pins should be as close to
the MOSFET’s gate as possible. Also the ground return loop should be as short as possible.
To minimize parasitic inductance-induced premature turn-off issue of the synchronous controller always
keep the PCB track length between ZXGD3101’s Drain input and MOSFET’s Drain to less than 10mm. Low
internal inductance MOSFET packages such as SO-8 and PolarPak are also recommended for high
switching frequency power conversion to minimize body diode conduction.
R1, Q1 D1 and C1 in Figure 1 are only required as a series drop-down regulator to maintain a stable Vcc
around 10V from a power supply output voltage greater than 15V.
External gate resistors are optional. They can be inserted to control the rise and fall time which may help
with EMI issues.
The proper selection of external resistors R
REF
and R
BIAS
is important to the optimum device operation.
Select a value for resistor R
REF
and R
BIAS
from Table 1 based on the desired Vcc value. This provides the
typical ZXGD3103’s detection threshold voltage of 10mV.
Table 1. Recommended resistor values for various supply voltages
V
CC
R
BIAS
R
REF
5V 1K6 2K0
10V 3K3 4K3
12V 3K9 5K1
15V 5K1 6K8