4 chipset, Peci [enabled, Inter(r) speedstep (tm) tech. [disabled – Asus Blitz Formula (Special Edition) User Manual
Page 100: North bridge chipset configuration, Configuration options: [enabled] [disabled
![4 chipset, Peci [enabled, Inter(r) speedstep (tm) tech. [disabled | North bridge chipset configuration, Configuration options: [enabled] [disabled | Asus Blitz Formula (Special Edition) User Manual | Page 100 / 166](/screens/312084/100.png)
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