Asus P5MT-MX/C - Manual (Page 81)

ASUS P5MT-MX/C 4-23
4.4.5 Chipset
The Chipset menu allows you to change the advanced chipset settings.
Select an item then press to display the sub-menu.
Manual DRAM Frequency
Setting or Auto by SPD. Advanced Chipset Settings
DRAM Frequency [Auto]
Configure DRAM Timing by SPD [Enabled]
Onboard LAN Boot ROM [Enabled]
PEG Port Configuration
PEG Port [Enabled]
PEG Port VC1 Map [TC7]
PEG Force x1 [Disabled]
Memory Remap Feature [Enabled]
DRAM Frequency [Auto]
Allows you to manually set the DRAM frequency. Setting to [Auto] allows
the BIOS to automatically set the DRAM frequency by Serial Presence
Detect (SPD). Configuration options: [Auto] [533 MHz] [667 MHz]
Configure DRAM Timing by SPD [Enabled]
When this item is enabled, the DRAM timing parameters are set according
to the DRAM SPD (Serial Presence Detect). When disabled, you can
manually set the DRAM timing parameters through the DRAM sub-items.
Configuration options: [Disabled] [Enabled]
The following sub-items appear when this item is Disabled.
DRAM CAS# Latency [5 Clocks]
Controls the latency between the SDRAM read command and the time
the data actually becomes available.
Configuration options: [5 Clocks] [4 Clocks] [3 Clocks] [6 Clocks]
DRAM RAS# Precharge [4 Clocks]
Controls the idle clocks after issuing a precharge command to the DDR
SDRAM. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks]
[5 Clocks]
DRAM RAS# to CAS# Delay [4 Clocks]
Controls the latency between the DDR SDRAM active command and
the read/write command. Configuration options: [2 Clocks] [3 Clocks]
[4 Clocks] [5 Clocks]
DRAM RAS# Activate to Precharge Delay [15 Clocks]
Configuration options: [1 Clock] ~ [15 Clocks]