Ocean Optics EMBED2000+ - Manual (Page 7)

EMBED2000+ Data Sheet
029-20000-005-05-201305 7
FPGA Communication
The SPI bus is the I/O communication link between the controlling device and FPGA. The FPGA is
considered the slave device and handles up to an 8MHz SPI clock for decoding MOSI bitstreams.
Data on MOSI is clocked in on the falling edge of the SPI clock, while data out to MISO is latched on
the rising edge.
SPI Communication Examples
Each read and write transfer is 24 clock pulses total consisting of 6 address bits, a null bit, a R/W bit
0/1 respectively, and 16 data bits.
The MOSI bitstream is decoded on the rising edge of each SPI_CLK. All values returned from a read
cycle transition on the falling edge of SPI_CLK.
Below is an example of a single generic SPI read/write cycle.
MOSI
MISO
SPI_CLK
SPI_CS
Address R/W
SPI Generic Read / Write Cycle
16-bit Read Data Address