Ocean Optics EMBED2000+ - Manual (Page 5)

EMBED2000+ Data Sheet
029-20000-005-05-201305 5
Communication and Interface
Initialization
On power up the FPGA loads its program contents from a dedicated external EEPROM that
configures the FPGA. After configuration the X_RESET pin must be strobed from low-high-low for a
minimum of 1us to initiate a global reset. X_RESET is an asynchronous active-high level sensitive
reset which does not place constraints on timing or signal duration. It is essential that the controlling
program waits for FPGA configuration before initiating the global reset.
The typical time needed for the attached PROM to configure the FPGA after power up is 100ms.
After issuing the X_RESET pulse configuration can be verified by reading the FPGA_VERSION
register.
Interface
The EMBED2000+ detector board contains a Xilinx® FPGA to handle detector clocking and analog-
to-digital results of pixel information. The FPGA is controlled via an industry standard SPI bus to
write and read all operating parameters as well as retrieving spectral data from the spectrometer.
Additionally, one Microchip® 25AA040A EEPROM and an Analog Devices® ADT7301 precision
centigrade temperature sensor are available on separate SPI chip selects for storage of calibration data
and detector temperature monitoring.
All chip select SPI devices are designed to operate on the same clock phase and polarity.