Rainbow Electronics DDS1693 User Manual

Page 4

DS1689/DS1693

4 of 32

AD0-AD7 (Multiplexed Bi-directional Address/Data Bus) - Multiplexed buses save pins because
address information and data information time-share the same signal paths. The addresses are present
during the first portion of the bus cycle and the same pins and signal paths are used for data in the second
portion of the cycle. Address/data multiplexing does not slow the access time of the DS1689 since the bus
change from address to data occurs during the internal RAM access time. Addresses must be valid prior
to the latter portion of ALE, at which time the DS1689/DS1693 latches the address. Valid write data must
be present and held stable during the latter portion of the

pulse. In a read cycle the DS1689/DS1693

outputs 8 bits of data during the latter portion of the

pulse. The read cycle is terminated and the bus

returns to a high impedance state as

transitions high. The address/data bus also serves as a bi-

directional data path for the external extended RAM.

ALE (RTC Address Strobe Input; active high) - A pulse on the address strobe pin serves to
demultiplex the bus. The falling edge of ALE causes the RTC address to be latched within the
DS1689/DS1693.

(RTC Read Input; active low) -

identifies the time period when the DS1689/DS1693 drives the

bus with RTC read data. The

signal is an enable signal for the output buffers of the clock.

(RTC Write Input; active low) - The

signal is an active low signal. The

signal defines

the time period during which data is written to the addressed register.

(RTC Chip Select Input; active low) - The Chip Select signal must be asserted low during a bus

cycle for the RTC portion of the DS1689/DS1693 to be accessed.

must be kept in the active state

during

and

timing. Bus cycles, which take place with ALE asserted but without asserting,

will latch addresses. However, no data transfer will occur.

IRQ

(Interrupt Request Output; open drain, active low) - The

IRQ

pin is an active low output of the

DS1689/DS1693 that can be tied to the interrupt input of a processor. The

IRQ

output remains low as

long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. To
clear the

IRQ

pin, the application software must clear all enabled flag bits contributing to

IRQ

’s active

state.

When no interrupt conditions are present, the

IRQ

level is in the high impedance state. Multiple

interrupting devices can be connected to an

IRQ

bus. The

IRQ

pin is an open drain output and requires an

external pull-up resistor.

CEI

(RAM Chip Enable Input; active low) -

CEI

should be driven low to enable the external RAM.

CEO

(RAM Chip Enable Output; active low) - When power is valid,

CEO

will equal

CEI

. When

power is not valid,

CEO

will be driven high regardless of

CEI

PWR

(Power-on Output; open drain, active low) - The

PWR

pin is intended for use as an on/off

control for the system power. With V

voltage removed from the DS1689/DS1693,

PWR

may be

automatically activated from a Kickstart input via the

pin or from a Wake-up interrupt. Once the

system is powered on, the state of

PWR

can be controlled via bits in the Dallas registers.