Rainbow Electronics DDS1693 User Manual

Page 18

DS1689/DS1693

18 of 32

Similarly, the kickstart feature is controlled through the Kickstart Interrupt Enable bit in extended control
register B (KSE, bank 1, 04BH).

A wake-up sequence will occur as follows: When wake-up is enabled via WIE = 1 while the system is
powered down (no V

voltage), the clock/calendar will monitor the current date for a match condition

with the date alarm register (bank 1, register 049H). In conjunction with the date alarm register, the hours,
minutes, and seconds alarm bytes in the clock/calendar register map (bank 0, registers 05H, 03H, and
01H) are also monitored. As a result, a wake-up will occur at the date and time specified by the date,
hours, minutes, and seconds alarm register values. This additional alarm will occur regardless of the
programming of the AIE bit (bank 0, register B, 0BH). When the match condition occurs, the

PWR

will automatically be driven low. This output can be used to turn on the main system power supply which
provides V

voltage to the DS1689/DS1693 as well as the other major components in the system. Also

at this time, the Wake-Up flag (WF, bank 1, register 04AH) will be set, indicating that a wake-up
condition has occurred.

A kickstart sequence will occur when kickstarting is enabled via KSE = 1. While the system is powered
down, the KS input pin will be monitored for a low going transition of minimum pulse width t

KSPW

. When

such a transition is detected, the

PWR

line will be pulled low, as it is for a wake-up condition. Also at this

time, the Kickstart Flag (KF, bank 1, register 04AH) will be set, indicating that a kickstart condition has
occurred.

The timing associated with both the wake-up and kickstarting sequences is illustrated in the Wake-Up /
Kickstart Timing Diagram in the Electrical Specifications section of this data sheet. The timing associated
with these functions is divided into 5 intervals, labeled 1-5 on the diagram.

The occurrence of either a kickstart or wake-up condition will cause the PWR pin to be driven low, as
described above. During interval 1, if the supply voltage on the DS1689/DS1693 V

pin rises above the

3-volt power-fail level before the power-on timeout period (t

POTO

) expires, then

PWR

will remain at the

active low level. If V

does not rise above the 3-volt power fail voltage in this time, then the

PWR

output pin will be turned off and will return to its high impedance level. In this event, the

IRQ

pin will

also remain tri-stated. The interrupt flag bit (either WF or KF) associated with the attempted power-on
sequence will remain set until cleared by software during a subsequent system power-on.

If V

is applied within the timeout period, then the system power-on sequence will continue as shown in

intervals 2-5 in the timing diagram. During interval 2,

PWR

will remain active and

IRQ

will be driven to

its active low level, indicating that either WF or KF was set in initiating the power-on. In the diagram

is assumed to be pulled up to the V

BAUX

supply. Also at this time, the PAB bit will be automatically

cleared to 0 in response to a successful power-on. The

PWR

line will remain active as long as the PAB

remains cleared to 0.

At the beginning of interval 3, the system processor has begun code execution and clears the interrupt
condition of WF and/or KF by writing 0s to both of these control bits. As long as no other interrupt within
the DS1689/DS1693 is pending, the

IRQ

line will be taken inactive once these bits are reset. Execution of

the application software may proceed. During this time, both the wake-up and kickstart functions may be
used to generate status and interrupts. WF will be set in response to a date, hours, and minutes match
condition. KF will be set in response to a low going transition on

. If the associated interrupt enable bit

is set (WIE and/or KSE) then the

IRQ

line will driven active low in response to enabled event. In