Rainbow Electronics MAX3798 - Manual (Page 8)

MAX3798
1.0625Gbps to 10.32Gbps, Integrated, Low-
Power SFP+ Limiting Amplifier and VCSEL Driver
8 _______________________________________________________________________________________
MAX3798
V CCR
LOS
MSEL
ROUT+
DISABLE
V CCD
V EER
BMAX
V EET
FAULT
TOUT+
V CCT
BIAS
1nF
0.1 μF
0.1 μF
1000pF
50 Ω
50 Ω
4.7k Ω
400 Ω
4.7k Ω
400 Ω
1k Ω
1000pF
1 μH
V CC
V CCR
V CCT
V CCD
0.1 μF
0.1 μF
V CCR
V CCT
V CCT
V CCD
1000pF
V CCT
OSCILLOSCOPE
V CCR
CONTROLLER
CONTROLLER
CONTROLLER
CONTROLLER
50 Ω
50
Ω
50
Ω
ROUT-
0.1 μF
50 Ω
50 Ω
SCL SDA CSEL TIN+
0.1 μF
50
Ω
TIN- BMON
CAZ1 CAZ2 RIN+
0.1 μF
50
Ω
RIN-
MMAX
TOUT-
0.1 μF
50 Ω
OSCILLOSCOPE
50 Ω
50 Ω
0.1 μF 0.1 μF
Figure 1. Test Circuit for VCSEL Driver Characterization
Note 5: Receiver deterministic jitter is measured with a repeating 2 31 - 1 PRBS equivalent pattern at 10.32Gbps. For 1.0625Gbps to
8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is defined as the arithmetic sum
of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ).
Note 6: Measured with a k28.5 pattern from 1.0625Gbps to 8.5Gbps. Measured with 2 31 - 1 PRBS at 10.32Gbps.
Note 7: Measurement includes an input AC-coupling capacitor of 100nF and C CAZ of 100nF. The signal at the input is switched
between two amplitudes: Signal_ON and Signal_OFF.
1) Receiver operates at sensitivity level plus 1dB power penalty.
a) Signal_OFF = 0
Signal_ON = (+8dB) + 10log(min_assert_level)
b) Signal_ON = (+1dB) + 10log(max_deassert_level)
Signal_OFF = 0
2) Receiver operates at overload.
Signal_OFF = 0
Signal_ON = 1.2V
P-P
max_deassert_level and the min_assert_level are measured for one LOS_THRESHOLD setting.
Note 8: Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and V CC
from +2.95V to +3.63V. Reference current measured at V CC = +3.2V, T A = +25°C.
Note 9: Transmitter deterministic jitter is measured with a repeating 2 7 - 1 PRBS, 72 0s, 2 7 - 1 PRBS, and 72 1s pattern at
10.32Gbps. For 1.0625Gbps to 8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is
defined as the arithmetic sum of PWD and PDJ.
Note 10: Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and V CC
from +2.85V to +3.63V. Reference current measured at V CC = +3.3V, T A = +25°C.