Rainbow Electronics MAX3580 - Manual (Page 17)

MAX3580
Direct-Conversion TV Tuner
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Write Cycle
When addressed with a write command, the MAX3580
allows the master to write to a single register or to multi-
ple successive registers.
A write cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX3580 issues an
ACK if the slave address byte is successfully received.
The bus master must then send to the slave the
address of the first register it wishes to write to. If the
slave acknowledges the address, the master can then
write one byte to the register at the specified address.
Data is written beginning with the most significant bit.
The MAX3580 again issues an ACK if the data is suc-
cessfully written to the register. The master can contin-
ue to write data to the successive internal registers with
the MAX3580 acknowledging each successful transfer,
or it can terminate transmission by issuing a STOP con-
dition. The write cycle does not terminate until the mas-
ter issues a STOP condition.
Figure 2 illustrates an example in which Registers 0
through 2 are written with 0x0E, 0xD8, and 0xE1,
respectively.
Read Cycle
When addressed with a read command, the MAX3580
allows the master to read back a single register or mul-
tiple successive registers.
A read cycle begins with the bus master issuing a
START condition followed by the 7 slave address bits
and a write bit (R/W = 0). The MAX3580 issues an ACK if
the slave address byte is successfully received. The bus
master must then send the address of the first register it
wishes to read. The slave acknowledges the address.
Then a START condition is issued by the master, fol-
lowed by the 7 slave address bits and a read bit (R/W =
1). The MAX3580 issues an ACK if the slave address
byte is successfully received. The MAX3580 starts send-
ing data MSB first with each SCL clock cycle. At the 9th
clock cycle, the master can issue an ACK, and continue
to read successive registers, or the master terminate the
transmission by issuing a NACK. The read cycle does
not terminate until the master issues a STOP condition.
Figure 3 illustrates an example in which Registers 0
through 2 are read back.
START
WRITE DEVICE
ADDRESS
R/ W
1100000
WRITE REGISTER
ADDRESS
0x00 0
ACK ACK
WRITE DATA TO
REGISTER 0x00
0x0E
ACK
WRITE DATA TO
REGISTER 0x01
0xD8
ACK
WRITE DATA TO
REGISTER 0x02
0xE1
ACK
STOP
Figure 2. Example: Write Registers 0 through 2 with 0x0E, 0xD8 and 0xE1, respectively.
S
T
A
R
T S
T
A
R
T
A
C
K A
C
K A
C
K A
C
K A
C
K
N
A
C
K S
T
O
P DEVICE
ADDRESS
DEVICE
ADDRESS
REG 00
DATA
REG 01
DATA
REG 02
DATA
REGISTER
ADDRESS
R/ W
11000000 00000000 11000000 xxxxxxxx xxxxxxxx xxxxxxxx 0 1
R/ W
Figure 3. Example: Receive data from read registers.