Rainbow Electronics MAX3580 - Manual (Page 16)

MAX3580
Direct-Conversion TV Tuner
16 ______________________________________________________________________________________
To Read Back Fuses
IMPORTANT NOTICE: When reading other addresses
than 8’h00 (the system trim bits), it is possible that the
data going to the bias cells will be disturbed due to the
architecture of the fuse bank. This means the bias cur-
rent could change while reading back fuse data.
1) Write 8’hXX to TFA. XX is the address of the fuse col-
umn you want to read.
2) Read 8’hXX from TFR. TFR is the Tracking Filter
Read Register.
3) Repeat steps 1 and 2 for other addresses.
2-Wire Serial Interface
The MAX3580 uses a 2-wire I 2 C*-compatible serial
interface consisting of a serial-data line (SDA) and a
serial-clock line (SCL). The serial interface allows com-
munication between the MAX3580 and the master at
clock frequencies up to 400kHz. The master initiates a
data transfer on the bus and generates the SCL signal
to permit data transfer. The MAX3580 behaves as slave
devices that transfer and receive data to and from the
master. Pull SDA and SCL high with external pullup
resistors (1kΩ or greater) for proper bus operation.
One bit is transferred during each SCL clock cycle. A
minimum of nine clock cycles are required to transfer a
byte in or out of the MAX3580 (8 bits and an ACK/NACK).
The data on SDA must remain stable during the high peri-
od of the SCL clock pulse. Changes in SDA while SCL is
high and stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high.
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the mas-
ter and the MAX3580 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master must reattempt
communication at a later time.
Slave Address
The MAX3580 has a 7-bit slave address that must be
sent to the device following a START condition to initi-
ate communication. The slave address is determined
by the state of the ADDR2 pin and is equal to
11000[ADDR2]0 (see Table 4). The eighth bit (R/W) fol-
lowing the 7-bit address determines whether a read or
write operation will occur.
The MAX3580 continuously awaits a START condition
followed by its slave address. When the device recog-
nizes its slave address, it acknowledges by pulling the
SDA line low for one clock period; it is ready to accept
or send data depending on the R/W bit (Figure 1).
*Purchase of I 2 C components of Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a
license under the Philips I 2 C Patent rights to use these components in an I 2 C system, provided that the system conforms to the I 2 C
Standard Specification as defined by Philips.
Table 4. Address Configuration
ADDRESS (WRITE/READ) ADDR2
C0/C1 HEX 0
C4/C5 HEX 1
SCL
SDA
1 2 3 4 5 6 7 8 9
S 1 1 0 0 0 0 R/ W ACK
SLAVE ADDRESS
ADDR2
Figure 1. MAX3580 Slave Address Byte