Rainbow Electronics MAX1301 User Manual
Page 28
MAX1300/MAX1301
Unipolar Offset Error
-FSR to 0V
When a zero-scale analog input voltage is applied to
the converter inputs, the digital output is all ones
(0xFFFF). Ideally, the transition from 0xFFFF to 0xFFFE
occurs at AGND1 - 0.5 LSB. Unipolar offset error is the
amount of deviation between the measured zero-scale
transition point and the ideal zero-scale transition point,
with all untested channels grounded.
0V to +FSR
When a zero-scale analog input voltage is applied to
the converter inputs, the digital output is all zeros
(0x0000). Ideally, the transition from 0x0000 to 0x0001
occurs at AGND1 + 0.5 LSB. Unipolar offset error is the
amount of deviation between the measured zero-scale
transition point and the ideal zero-scale transition point,
with all untested channels grounded.
Bipolar Offset Error
When a zero-scale analog input voltage is applied to the
converter inputs, the digital output is a one followed by
all zeros (0x8000). Ideally, the transition from 0x7FFF to
0x8000 occurs at (2
N-1
- 0.5)LSB. Bipolar offset error is
the amount of deviation between the measured midscale
transition point and the ideal midscale transition point,
with untested channels grounded.
Gain Error
When a positive full-scale voltage is applied to the con-
verter inputs, the digital output is all ones (0xFFFF). The
transition from 0xFFFE to 0xFFFF occurs at 1.5 LSB
below full scale. Gain error is the amount of deviation
between the measured full-scale transition point and
the ideal full-scale transition point with the offset error
removed and all untested channels grounded.
Unipolar Endpoint Overlap
Unipolar endpoint overlap is the change in offset when
switching between complementary input voltage
ranges. For example, the difference between the volt-
age that results in a 0xFFFF output in the -6V to 0V
input voltage range and the voltage that results in a
0x0000 output in the 0 to +6V input voltage range is the
unipolar endpoint overlap. The unipolar endpoint over-
lap is positive for the MAX1300/MAX1301, preventing
loss of signal or a dead zone when switching between
adjacent analog input voltage ranges.
Small-Signal Bandwidth
A 100mV
P-P
sine wave is applied to the ADC, and the
input frequency is then swept up to the point where the
amplitude of the digitized conversion result has
decreased by -3dB.
Full-Power Bandwidth
A 95% of full-scale sine wave is applied to the ADC,
and the input frequency is then swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB.
Common-Mode Rejection Ratio (CMRR)
CMRR is the ability of a device to reject a signal that is
“common” to or applied to both input terminals. The
common-mode signal can be either an AC or a DC sig-
nal or a combination of the two. CMR is expressed in
decibels. Common-mode rejection ratio is the ratio of
the differential signal gain to the common-mode signal
gain. CMRR applies only to differential operation.
Power-Supply Rejection Ratio (PSRR)
PSRR is the ratio of the output-voltage shift to the
power-supply-voltage shift for a fixed input voltage. For
the MAX1300/MAX1301, AV
DD1
can vary from 4.75V to
5.25V. PSRR is expressed in decibels and is calculated
using the following equation:
For the MAX1300/MAX1301, PSRR is tested in bipolar
operation with the analog inputs grounded.
Aperture Jitter
Aperture jitter, t
AJ
, is the statistical distribution of the
variation in the sampling instant (Figure 21).
Aperture Delay
Aperture delay, t
AD
, is the time from the falling edge of
SCLK to the sampling instant (Figure 21).
Signal-to-Noise Ratio (SNR)
SNR is computed by taking the ratio of the RMS signal
to the RMS noise. RMS noise includes all spectral com-
ponents to the Nyquist frequency excluding the funda-
mental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise plus distortion. RMS noise plus
distortion includes all spectral components to the
Nyquist frequency excluding the fundamental and the
DC offset.
SINAD dB
Signal
Noise
RMS
RMS
(
)
log
=
×
20
PSRR dB
V
V
V
V
V
V
OUT
OUT
[
]
log
.
.
( .
)
( .
)
=
×
−
−
20
5 25
4 75
5 25
4 75
8-/4-Channel, ±12V Multirange Inputs,
Serial 16-Bit ADCs
28
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