Rainbow Electronics MAX1301 - Manual (Page 14)

MAX1300/MAX1301
Power Supplies
To maintain a low-noise environment, the MAX1300 and
MAX1301 provide separate power supplies for each
section of circuitry. Table 1 shows the four separate
power supplies. Achieve optimal performance using
separate AV
DD1 , AV DD2 , DV DD , and DV DDO supplies.
Alternatively, connect AV DD1 , AV DD2 , and DV DD
together as close to the device as possible for a conve-
nient power connection. Connect AGND1, AGND2,
AGND3, DGND, and DGNDO together as close to the
device as possible. Bypass each supply to the corre-
sponding ground using a 0.1µF capacitor (Table 1). If
significant low-frequency noise is present, add a 10µF
capacitor in parallel with the 0.1µF bypass capacitor.
Converter Operation
The MAX1300/MAX1301 ADCs feature a fully differen-
tial, successive-approximation register (SAR) conver-
sion technique and an on-chip T/H block to convert
voltage signals into a 16-bit digital result. Both single-
ended and differential configurations are supported
with programmable unipolar and bipolar signal ranges.
Track-and-Hold Circuitry
The MAX1300/MAX1301 feature a switched-capacitor
T/H architecture that allows the analog input signal to be
stored as charge on sampling capacitors. See Figures 2,
3, and 4 for T/H timing and the sampling instants for
each operating mode. The MAX1300/MAX1301 analog
input circuitry buffers the input signal from the sampling
capacitors, resulting in a constant input impedance with
varying input voltage (Figure 5).
Analog Input Circuitry
Select differential or single-ended conversions using the
associated analog input configuration byte (Table 2).
The analog input signal source must be capable of dri-
ving the ADC’s 17k
Ω input resistance (Figure 6).
Figure 6 shows the simplified analog input circuit. The
analog inputs are ±16.5V fault tolerant and are protected
by back-to-back diodes. The summing junction voltage,
V
SJ , is a function of the channel’s input common-
mode voltage:
As a result, the analog input impedance is relatively con-
stant over input voltage as shown in Figure 5.
V
R
R R
V
R
R R
V
SJ CM
. =
+

 

Ч + +
+

 
 
 

Ч
1
1 2
2 375 1
1
1 2
8-/4-Channel, ±12V Multirange Inputs,
Serial 16-Bit ADCs
14 ______________________________________________________________________________________
Table 1. MAX1300/MAX1301 Power Supplies and Bypassing
POWER
SUPPLY/GROUND
SUPPLY VOLTAGE
RANGE (V)
TYPICAL SUPPLY
CURRENT (mA)
CIRCUIT SECTION BYPASSING
DV DDO /DGNDO 2.7 to 5.25 0.2 Digital I/O 0.1µF to DGNDO
AV DD2 /AGND2 4.75 to 5.25 17.5 Analog Circuitry 0.1µF to AGND2
AV DD1 /AGND1 4.75 to 5.25 3.0 Analog Circuitry 0.1µF to AGND1
DV
DD
/DGND 4.75 to 5.25 0.9 Digital Control Logic and Memory 0.1µF to DGND
Table 2. Analog Input Configuration Byte
BIT
NUMBER
NAME DESCRIPTION
7 START Start Bit. The first logic 1 after CS goes low defines the beginning of the analog input configuration byte.
6 C2
5 C1
4 C0
Channel-Select Bits. SEL[2:0] select the analog input channel to be configured (Tables 4 and 5).
3 DIF/SGL
Differential or Single-Ended Configuration Bit. DIF/SGL = 0 configures the selected analog input channel
for single-ended operation. DIF/SGL = 1 configures the channel for differential operation. In single-ended
mode, input voltages are measured between the selected input channel and AGND1, as shown in
Table 4. In differential mode, the input voltages are measured between two input channels, as shown in
Table 5. Be aware that changing DIF/SGL adjusts the FSR, as shown in Table 6.
2 R2
1 R1
0 R0
Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.