Rainbow Electronics MAX1338 - Manual (Page 5)

MAX1338
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
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ELECTRICAL CHARACTERISTICS (continued)
(AV DD = DV DD = +5.0V, DRV DD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, f CLK = 5MHz, input range =
±10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0µF and 0.1µF from COM1 to AGND,
0.1µF from REFP1 to AGND, 0.1µF from REFN1 to AGND, 1.0µF from REFP1 to REFN1. Typical values are at T
A = +25°C. T A = T MIN
to T MAX , unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Figures 4, 5, and 6)
Internal clock 2.9 3.2 3.5 µs
Time to First Conversion Result t EOC1
External clock 16
CLK
Cycles
Internal clock 600 ns
Time to Subsequent Conversions t NEXT
External clock 3
CLK
Cycles
CONVST Pulse-Width Low t CONVST 0.1 µs
CS Pulse Width t CS 30 ns
RD Pulse-Width Low t RDL 30 ns
RD Pulse-Width High t RDH 30 ns
WR Pulse-Width Low t WRL 30 ns
CS to WR Setup Time t CTW 0 ns
WR to CS Hold Time t WTC 0 ns
CS to RD Setup Time t CTR 0 ns
RD to CS Hold Time t RTC 0 ns
Data Access Time
(RD Low to Valid Data)
t ACC Figure 1 30 ns
Bus Relinquish Time
(RD High to D_ High-Z)
t REQ Figure 1 5 30 ns
CLK Rise to End-of-Conversion
(EOC) Rise/Fall Delay
t EOCD 20 ns
CLK Rise to End-of-Last-
Conversion (EOLC) Fall Delay
t
EOLCD
20 ns
CONVST Rise to EOLC Fall Delay t CVEOLCD 20 ns
Internal clock 180 200 ns
EOC Pulse-Width Low t EOC
External clock 1
CLK
Cycle
Wake-Up Time From Standby 7 µs
Wake-Up Time From Shutdown All bypass capacitors discharged 5 ns