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Electrical characteristics (continued) – Rainbow Electronics MAX1183 User Manual

Page 4

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MAX1183

Dual 10-Bit, 40Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs

4

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ELECTRICAL CHARACTERISTICS (continued)

(V

DD

= +3V, OV

DD

= +2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through

a 10k

Ω resistor, V

IN

= 2Vp-p (differential with respect to COM), C

L

= 10pF at digital outputs (Note 5), f

CLK

= 40MHz, T

A

= T

MIN

to

T

MAX

, unless otherwise noted. Typical values are at T

A

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)

CLK

0.8 x

V

DD

Input High Threshold

V

IH

PD, OE, SLEEP, T/B

0.8 x

OV

DD

V

CLK

0.2 x

V

DD

Input Low Threshold

V

IL

PD, OE, SLEEP, T/B

0.2 x

OV

DD

V

Input Hysteresis

V

HYST

0.1

V

I

IH

V

IH

= OV

DD

or V

DD

(CLK)

±5

Input Leakage

I

IL

V

IL

= 0

±5

µA

Input Capacitance

C

IN

5

pF

DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)

Output Voltage Low

V

OL

I

SINK

= -200µA

0.2

V

Output Voltage High

V

OH

I

SOURCE

= 200µA

OV

DD

- 0.2

V

Three-State Leakage Current

I

LEAK

OE = OV

DD

±10

µA

Three-State Leakage
Capacitance

C

OUT

OE = OV

DD

5

pF

POWER REQUIREMENTS

Analog Supply Voltage Range

V

DD

2.7

3

3.6

V

Output Supply Voltage Range

OV

DD

1.7

2.5

3.6

V

Operating, f

INA or B

= 20MHz at -0.5dB FS

40

60

Sleep mode

2.8

mA

Analog Supply Current

I

VDD

Shutdown, clock idle, PD = OE = OV

DD

1

15

µA

Operating, C

L

= 15pF,

f

INA or B

= 20MHz at -0.5dB FS

5.8

mA

Sleep mode

100

Output Supply Current

I

OVDD

Shutdown, clock idle, PD = OE = OV

DD

2

10

µA

Operating, f

INA or B

= 20MHz at -0.5dB FS

120

180

Sleep mode

8.4

mW

Power Dissipation

PDISS

Shutdown, clock idle, PD = OE = OV

DD

3

45

µW

Offset

±0.2

mV/V

Power-Supply Rejection

PSRR

Gain

±0.1

%V

TIMING CHARACTERISTICS

CLK Rise to Output Data Valid

t

DO

Figure 3 (Note 3)

5

8

ns

Output Enable Time

t

ENABLE

Figure 4

10

ns

Output Disable Time

t

DISABLE

Figure 4

1.5

ns