Rainbow Electronics MAX1800 - Manual (Page 18)

MAX1800
Digital Camera Step-Up
Power Supply
18 ______________________________________________________________________________________
4) Place the compensation zero at the same frequency
as the maximum output pole frequency (in Hz):
Solving for C C :
Use values of C
C
less than 10nF. If the above calcula-
tion determines that the capacitor should be greater
than 10nF, use C
C = 10nF, skip step 4 , and proceed to
step 5.
4) Determine the crossover frequency (in Hz):
To maintain at least a 10dB gain margin, make sure
that the crossover frequency is less than or equal to
1/3 of the output capacitor ESR zero frequency, or:
3f C
≤ Z
O
or:
If this is not the case, go to step 5 to reduce the error
amplifier high-frequency gain to decrease the
crossover frequency.
5) The high-frequency gain may be reduced, thus
reducing the crossover frequency, as long as the
zero due to the compensation network remains at
or below the crossover frequency. In this case:
and:
Choose C
OUT
, R
C
, and C
C
to simultaneously satisfy
both equations.
Continuous Inductor Current
For continuous inductor current, there are two condi-
tions that change, requiring different compensation.
The response of the control loop includes a right-half-
plane zero and a complex pole pair due to the inductor
and output capacitor. For stable operation, the con-
troller loop gain must drop below unity (0dB) at a much
lower frequency than the right-half-plane zero frequen-
cy. The zero arising from the ESR of the output capaci-
tor is typically used to compensate the control circuit
by increasing the phase near the crossover frequency,
increasing the phase margin. If a low-value, low-ESR
output capacitor (such as a ceramic capacitor) is used,
the ESR-related zero occurs at too high a frequency
and does not increase the phase margin. In this case,
use a lower value inductor so that it operates with dis-
continuous current (see the Discontinuous Inductor
Current section).
For continuous inductor current, the gain of the voltage
divider is A
VDV = V REF / V OUT, and the DC gain of the
error amplifier is A VEA = 2000. The gain through the
PWM controller in continuous current is:
Thus, the total DC loop gain is:
The complex pole pair due to the inductor and output
capacitor occurs at the frequency (in Hz):
The pole and zero due to the compensation network at
COMP occur at the frequencies (in Hz):
The frequency (in Hz) of the zero due to the ESR of the
output capacitor is:
The right-half-plane zero frequency (in Hz) is:
Z
(1 - D) R
2 L
RHP
LOAD
2
=
π
Z
C ESR
O
OUT
=
1
2 π
Z
R C
C
C C
=
1
2
π
P
G
C C
C
EA
C C
= =
× 4000
1
4 10
7 π π
P
V
V LC
O
OUT
IN OUT
=
2 π
A
V
V
VDC
OUT
IN
=
2000
A
V
V V
VO
OUT
IN REF
=
2
f
V
C
1
C
C
REF EA C
OUT C C
= ≥
G R
D R
π π
1
2
ESR
D
6 V
EA C ERF
≤
G R
ESR
D
6 V
ERF
≤ D
f
V
C
C
REF
OUT
=
π D
C C V
V - V
I V - V
C OUT OUT
OUT IN
C OUT(MAX) OUT IN
=







 R 2( )
Z
1 2(V - V
V - V C
C
C C
OUT IN)
OUT IN LOAD(MIN) OUT
= =
2 2 π π R C R ( )