Rainbow Electronics MAX3625В - Manual (Page 5)

MAX3625B
Low-Jitter, Precision Clock
Generator with Three Outputs
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Pin Description
PIN NAME FUNCTION
1, 24
SELB0,
SELB1
LVCMOS/LVTTL Inputs. Control NB divider setting. Has 50k input impedance. See Table 2 for more
information.
2 BYPASS
LVCMOS/LVTTL Input (Active Low). Connect low to bypass the internal PLL. Connect high or leave
open for normal operation. When in bypass mode the output dividers are set to divide by 1. Has
internal 75k
pullup to V
CC .
3 MR
LVCMOS/LVTTL Input. Master reset input. Pulse high for > 1μs to reset all dividers. Has internal 75k
pulldown to GND. Not required for normal operation.
4 V CCO_A Power Supply for QA Clock Output. Connect to +3.3V.
5 QA Noninverting Clock Output, LVPECL
6 QA Inverting Clock Output, LVPECL
7 QB_OE
LVCMOS/LVTTL Input. Enables/disables QB clock outputs. Connect pin high or leave open to enable
LVPECL clock outputs QB0 and QB1. Connect low to set QB0 and QB1 to a logic 0. Has internal 75k
pullup to V
CC
.
8 QA_OE
LVCMOS/LVTTL Input. Enables/disables the QA clock output. Connect high or leave open to enable the
LVPECL clock output QA. Connect low to set QA to a logic 0. Has internal 75k
pullup to V
CC .
9 FB_SEL
LVCMOS/LVTTL Input. Controls M divider setting. See Table 3 for more information. Has internal 75k
pulldown to GND.
Pin Configuration
+
TOP VIEW
MAX3625B
TSSOP
21
4
QB0
V
CCO_A
22
3
QB0
MR
23
2
V
CCO_B
BYPASS
24
1
SELB1
SELB0
18
7
IN_SEL
QB_OE
19
6
QB1
QA
17
8
REF_IN
QA_OE
16
9
X_IN
FB_SEL
15
10
X_OUT
V
CCA
14
11
GND
V
CC
13
12
SELA1
SELA0
20
5
QB1
QA
*EP
*EXPOSED PAD MUST BE SOLDERED TO GROUND FOR PROPER
THERMAL AND ELECTRICAL OPERATION.