Ds1870 ldmos rf power-amplifier bias controller – Rainbow Electronics DS1870 User Manual
Page 22
DS1870
LDMOS RF Power-Amplifier Bias
Controller
22
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PWE
PWE
memory that can be written are addresses 78h to 7Fh. This includes the PWE and Table_Select
locations. All memory is readable regardless of the PWE value.
TBL Sel
to this register grants access to the corresponding table.
TABLE 1 (CONFIGURATION)
Config
Password
EEPROM memory is write-protected when PWE does not match thisregister.
LUT Sel
a) VD2
A one selects the V
D
input to control the drain LUT indexing for POT2 (Table 5). A zero
selects the I
D2
input.
b) VD1
A one selects the V
D
input to control the drain LUT indexing for POT1 (Table 4). A zero
selects the I
D1
input.
Fault Ena
a) Temp Ena
Temperature measurements, outside the threshold limits, are enabled to create an
active interrupt on the FAULT pin.
b) Vcc Ena
V
CC
measurements, outside the threshold limits, are enabled to create an active
interrupt on the FAULT pin.
c) VD Ena
V
D
measurements, outside the threshold limits, are enabled to create an active
interrupt on the FAULT pin.
d) ID1 Ena
I
D1
measurements, outside the threshold limits, are enabled to create an active
interrupt on the FAULT pin.
e) ID2 Ena
I
D2
measurements, outside the threshold limits, are enabled to create an active
interrupt on the FAULT pin.
Scale
0
Vcc Scale
CC
measurements. The V
CC
gain is
factory trimmed to 6.5535V FS.
VD Scale
D
measurements. The V
D
gain is
factory trimmed to 2.500V FS.
ID1 Scale
D1
measurements. The I
D1
gain is
factory trimmed to 0.5V FS.
Scale
1
ID2 Scale
D2
measurements. The I
D2
gain is
factory trimmed to 0.5V FS.
Offset
0
Vcc Offset
CC
measurement
VD Offset
D
measurement.
ID1 Offset
D1
measurement.
Offset
1
ID2 Offset
D2
measurement.
Temp Offset
LUT Index