Rainbow Electronics DS89C450 - Manual (Page 29)

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
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The following diagrams illustrate the timing relationship for external data memory access in full speed (stretch value
= 0), in the default stretch setting (stretch value = 1), and slow data memory accessing (stretch value = 4), when
the system clock is in divide-by-1 mode (CD1:CD0 = 10b).
Figure 8. Nonpage Mode, External Data Memory Access (Stretch = 0, CD1:CD2 = 10)
ALE
Port 0
XTAL1
PSEN
RD/WR
MOVX INST A DATA A A
A A
Port 2
MOVX Instruction
1st Machine Cycle 2nd Machine Cycle
MOVX
Instruction
Fetch
Memory
Access
Stretch = 0
Figure 9. Nonpage Mode, External Data Memory Access (Stretch = 1, CD1:CD2 = 10)
ALE
Port 0
XTAL1
PSEN
RD/WR
MOVX INST A DATA A A
A A
Port 2
MOVX Instruction
1st Machine Cycle 2nd Machine Cycle
MOVX
Instruction
Fetch
Memory Access
Stretch = 1
3rd Machine Cycle