Rainbow Electronics AT89C51RC - Manual (Page 8)

AT89C51RC
8
Hardware Watchdog Timer
(One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations
where the CPU may be subjected to software upsets. The
WDT consists of a 14-bit counter and the WatchDog Timer
Reset (WDTRST) SFR. The WDT is defaulted to disable
from exiting reset. To enable the WDT, a user must write
01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, it will
increment every machine cycle while the oscillator is run-
ning. There is no way to disable the WDT except through
reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse
at the RST pin.
Using the WDT
To enable the WDT, a user must write 01EH and 0E1H in
sequence to the WDTRST register (SFR location 0A6H).
When the WDT is enabled, the user needs to service it by
writing 01EH and 0E1H to WDTRST to avoid a WDT over-
flow. The 14-bit counter overflows when it reaches 16383
(3FFFH), and this will reset the device. When the WDT is
enabled, it will increment every machine cycle while the
oscillator is running. This means the user must reset the
WDT at least every 16383 machine cycles. To reset the
WDT the user must write 01EH and 0E1H to WDTRST.
WDTRST is a write-only register. The WDT counter cannot
be read or written. When WDT overflows, it will generate an
output RESET pulse at the RST pin. The RESET pulse
duration is 98xTOSC, where TOSC=1/FOSC. To make the
best use of the WDT, it should be serviced in those sec-
tions of code that will periodically be executed within the
time required to prevent a WDT reset.
WDT During Power-down and Idle
In Power-down mode the oscillator stops, which means the
WDT also stops. While in Power-down mode, the user
does not need to service the WDT. There are two methods
of exiting Power-down mode: by a hardware reset or via a
level-activated external interrupt which is enabled prior to
entering Power-down mode. When Power-down is exited
with hardware reset, servicing the WDT should occur as it
normally does whenever the AT89C51RC is reset. Exiting
Power-down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabi-
lize. When the interrupt is brought high, the interrupt is ser-
viced. To prevent the WDT from resetting the device while
the interrupt pin is held low, the WDT is not started until the
interrupt is pulled high. It is suggested that the WDT be
reset during the interrupt service for the interrupt used to
exit Power-down mode.
To ensure that the WDT does not overflow within a few
states of exiting Power-down, it is best to reset the WDT
just before entering Power-down mode.
Before going into the IDLE mode, the WDIDLE bit in SFR
AUXR is used to determine whether the WDT continues to
count if enabled. The WDT keeps counting during IDLE
(WDIDLE bit = 0) as the default state. To prevent the WDT
from resetting the AT89C51RC while in IDLE mode, the
user should always set up a timer that will periodically exit
IDLE, service the WDT, and reenter IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in
IDLE mode and resumes the count upon exit from IDLE.
UART
The UART in the AT89C51RC operates the same way as
the UART in the AT89C51 and AT89C52. For further infor-
mation, see the December 1997 Microcontroller Data Book,
page 2-48, section titled, “Serial Interface”.
Timer 0 and 1
Timer 0 and Timer 1 in the AT89C51RC operate the same
way as Timer 0 and Timer 1 in the AT89C51 and AT89C52.
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either
a timer or an event counter. The type of operation is
selected by bit C/T2 in the SFR T2CON (shown in Table 2).
Timer 2 has three operating modes: capture, auto-reload
(up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 4.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the
Timer function, the TL2 register is incremented every
machine cycle. Since a machine cycle consists of 12
oscillator periods, the count rate is 1/12 of the oscillator
frequency.
In the Counter function, the register is incremented in
response to a 1-to-0 transition at its corresponding external
input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples
show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in which
Table 4. Timer 2 Operating Modes
RCLK +TCLK CP/RL2 TR2 MODE
0 0 1 16-bit Auto-reload
0 1 1 16-bit Capture
1 X 1 Baud Rate Generator
X X 0 (Off)