Rainbow Electronics DS2422 - Manual (Page 2)

DS2422/DS2423
2 of 25
triggered by inputs A and B, respectively, increment with every low-going pulse on their input. All
counters are read-only. They are automatically cleared to 0 when the battery is connected.
The battery-backed memory offers a simple solution to storing and retrieving information pertaining to
the equipment where the DS242X is installed and its frequency of use. The scratchpad is an additional
page that acts as a buffer when writing to memory. Data is first written to the scratchpad where it may be
read back for verification. A copy scratchpad command will then transfer the data to memory. This
process ensures data integrity when modifying the memory. A 64-bit registration number is factory
lasered into each DS242X to provide a guaranteed unique identity which allows for absolute traceability
and acts as node address if multiple DS242X are connected in parallel to form a local network. Data is
transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return.
The DS242X 1-Wire RAM with Counters can store encrypted data. The unique registration number and
the page write cycle counter(s) prevent unauthorized manipulation of data stored in a page with a write
cycle counter associated.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS242X. The DS242X has four main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad,
3) 1024-bit (DS2422) or 4096-bit (DS2423) SRAM, and 4) three (DS2422) or four (DS2423) 32-bit read-
only counters. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. Each of these
counters is associated with one of the 256-bit memory pages. The three counters of the DS2422 are
associated with pages 1 to 3; the four counters of the DS2423 are associated with pages 12 to 15. The
contents of the counter is read together with the memory data using a special command. The bus master
must first provide one of the six ROM Function Commands: 1) Read ROM, 2) Match ROM, 3) Search
ROM, 4) Skip ROM, 5) Overdrive-Skip ROM or 6) Overdrive-Match ROM. Upon completion of an
Overdrive ROM command byte executed at standard speed, the device will enter Overdrive mode where
all subsequent communication occurs at a higher speed. The protocol required for these ROM function
commands is described in Figure 9. After a ROM function command is successfully executed, the
memory functions become accessible and the master may provide any one of the five memory function
commands. The protocol for these memory function commands is described in Figure 7. All data is read
and written least significant bit first.
PARASITE POWER
The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry steals power whenever
the I/O input is high. I/O will provide sufficient power as long as the specified timing and voltage
requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input,
lithium is conserved, and 2) if the battery is exhausted for any reason, the ROM may still be read
normally.
64-BIT LASERED ROM
Each DS242X contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits (See Figure 3).
The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates
as shown in Figure 4. The polynomial is X
8 + X 5 + X 4 + 1. Additional information about the Dallas 1-
Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton ® Standards.
The shift register bits are initialized to 0. Then starting with the least significant bit of the family code,
one bit at a time is shifted in. After the 8
th bit of the family code has been entered, then the serial number
iButton is a registered trademark of Dallas Semiconductor.