Wire signaling, Read/write time slots – Rainbow Electronics DS2422 User Manual
Page 19
DS2422/DS2423
19 of 25
1-WIRE SIGNALING
The DS242X requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read
Data. The bus master initiates all these signals except Presence Pulse. The DS242X can communicate at
two different speeds, regular speed and Overdrive speed. If not explicitly set into the Overdrive mode, the
DS242X will communicate at regular speed. While in Overdrive mode the fast timing applies to all
waveforms.
The initialization sequence required to begin any communication with the DS242X is shown in Figure 10.
A Reset Pulse followed by a Presence Pulse indicates the DS242X is ready to send or receive data given
the correct ROM command and memory function command. The bus master transmits (TX) a Reset
Pulse (t
RSTL
, minimum 480 µs at regular speed, 48 µs at Overdrive speed). The bus master then releases
the line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor.
After detecting the rising edge on the data pin, the DS242X waits (t
PDH
, 15-60µs at regular speed, 2-6µs
at Overdrive speed) and then transmits the Presence Pulse (t
PDL
, 60-240µs at regular speed, 8-24µs at
Overdrive speed).
A Reset Pulse of 480µs or longer will exit the Overdrive mode returning the device to regular speed. If
the DS242X is in Overdrive mode and the Reset Pulse is no longer than 80µs the device will remain in
Overdrive mode.
Read/Write Time Slots
The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS242X to the master
by triggering a delay circuit in the DS242X. During write time slots, the delay circuit determines when
the DS242X will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay
circuit determines how long the DS242X will hold the data line low overriding the 1 generated by the
master. If the data bit is a “1”, the device will leave the read data time slot unchanged.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10