Rainbow Electronics DS2417 - Manual (Page 7)

DS2417
7 of 15
HARDWARE CONFIGURATION Figure 6
RX
TX
Open Drain
Port Pin
5 µA
Typ.
DS2417 1-WIRE PORT
RX = RECEIVE
TX = TRANSMIT
BUS MASTER VPUP
DATA
RX
TX
MOSFET
100 W
5 k W
Typ.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the
DS2417 is a slave device. The bus master is typically a microcontroller. The discussion of this bus
system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signaling (signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state
during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For a
more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain or 3-state outputs. The 1-Wire input of the DS2417 is open drain with an internal circuit equivalent
to that shown in Figure 6. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The
1-Wire bus has a maximum data rate of 16.3kbits per second and requires a pullup resistor of approxi-
mately 5k
W.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 120
ms, one or more of the devices on the bus may be reset. Since the DS2417 gets all its
energy for operation through its V
DD
pin it will NOT perform a power-on reset if the 1-Wire bus is low
for an extended time period.
TRANSACTION SEQUENCE
The protocol for accessing the DS2417 via the 1-Wire port is as follows:
§ Initialization
§ ROM Function Command
§ Clock Function Command