Rainbow Electronics MAX17101 - Manual (Page 26)

MAX17101
Dual Quick-PWM, Step-Down Controller
with Low-Power LDO, RTC Regulator
26 ______________________________________________________________________________________
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and fast-feed-
back loop instability. Double-pulsing occurs due to
noise on the output or because the ESR is so low that
there is not enough voltage ramp in the output voltage
signal. This “fools” the error comparator into triggering
a new cycle immediately after the 400ns minimum off-
time period has expired. Double-pulsing is more annoy-
ing than harmful, resulting in nothing worse than
increased output ripple. However, it can indicate the
possible presence of loop instability due to insufficient
ESR. Loop instability results in oscillations at the output
after line or load steps. Such perturbations are usually
damped, but can cause the output voltage to rise
above or fall below the tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (I
RMS ) imposed by the switching currents:
For most applications, nontantalum chemistries (ceramic,
aluminum, or OS-CON) are preferred due to their resis-
tance to power-up surge currents typical of systems
with a mechanical switch or connector in series with the
input. If the MAX17101 is operated as the second stage
of a two-stage power conversion system, tantalum input
capacitors are acceptable. In either configuration,
choose a capacitor that has less than 10°C tempera-
ture rise at the RMS input current for optimal reliability
and lifetime.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability when
using high-voltage (> 20V) AC adapters. Low-current
applications usually require less attention.
The high-side MOSFET (N H ) must be able to dissipate
the resistive losses plus the switching losses at both
V
IN(MIN) and V IN(MAX) . Ideally, the losses at V IN(MIN)
should be roughly equal to the losses at V IN(MAX) , with
lower losses in between. If the losses at V
IN(MIN)
are
significantly higher, consider increasing the size of N H .
Conversely, if the losses at V IN(MAX) are significantly
higher, consider reducing the size of N H . If V IN does
not vary over a wide range, maximum efficiency is
achieved by selecting a high-side MOSFET (N
H ) that
has conduction losses equal to the switching losses.
Choose a low-side MOSFET (N L ) that has the lowest
possible on-resistance (R DS(ON) ), comes in a moder-
ate-sized package (i.e., 8-pin SO, DPAK, or D 2 PAK),
and is reasonably priced. Ensure that the MAX17101
DL_ gate driver can supply sufficient current to support
the gate charge and the current injected into the para-
sitic drain-to-gate capacitor caused by the high-side
MOSFET turning on; otherwise, cross-conduction prob-
lems can occur. Switching losses are not an issue for
the low-side MOSFET since it is a zero-voltage
switched device when used in the step-down topology.
Power-MOSFET Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (N
H ), the worst-
case power dissipation due to resistance occurs at
minimum input voltage:
Generally, use a small high-side MOSFET to reduce
switching losses at high input voltages. However, the
R
DS(ON)
required to stay within package power-dissi-
pation often limits how small the MOSFET can be. The
optimum occurs when the switching losses equal the
conduction (R
DS(ON) ) losses. High-side switching loss-
es do not become an issue until the input is greater
than approximately 15V.
Calculating the power dissipation in high-side
MOSFETs (N
H ) due to switching losses is difficult, since
it must allow for difficult-to-quantify factors that influ-
ence the turn-on and turn-off times. These factors
include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PCB layout
characteristics. The following switching loss calculation
provides only a very rough estimate and is no substi-
tute for breadboard evaluation, preferably including
verification using a thermocouple mounted on N
H
:
PD N Switching
V I f Q
I
V C f
H
MAX LOAD SW G SW
GATE
IN OSS SW
( )
( ) ( ) =
⎛
⎝⎜ ⎞
⎠⎟
+
⎛
⎝
⎜
⎞
⎠
⎟
2
2
PD N sistive
V
V
I R
H
OUT
IN
LOAD DS O
( Re )
(
=
⎛
⎝⎜ ⎞
⎠⎟
( ) 2
N N)
I I
V V V
V
RMS LOAD
OUT IN OUT
IN
=
−
⎛
⎝
⎜
⎞
⎠
⎟
( )