Rainbow Electronics MAX9217 - Manual (Page 13)

MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
______________________________________________________________________________________ 13
Power-Down and Power-Off
Driving PWRDWN low stops the PLL, switches out the
integrated 100
Ω output termination, and puts the output
in high impedance to ground and differentially. With
PWRDWN
≤ 0.3V and all LVTTL/LVCMOS inputs ≤ 0.3V or
≥ V
CCIN - 0.3V, supply current is reduced to 50µA or less.
Driving PWRDWN high starts PLL lock to PCLK_IN and
switches in the 100
Ω output termination resistor. The
LVDS output is not driven until the PLL locks. The LVDS
output is high impedance to ground and 100
Ω differen-
tial. The 100
Ω integrated termination pulls OUT+ and
OUT- together while the PLL is locking so that V OD = 0V.
If V CC = 0, the output resistor is switched out and the LVDS
outputs are high impedance to ground and differentially.
PLL Lock Time
The PLL lock time is set by an internal counter. The lock
time is 16,385 PCLK_IN cycles. Power and clock should
be stable to meet the lock-time specification.
Input Buffer Supply
The single-ended inputs (RGB_IN[17:0], CNTL_IN[8:0],
DE_IN, RNG0, RNG1, MOD0, MOD1, PCLK_IN, and
PWRDWN) are powered from V
CCIN . V CCIN can be
connected to a 1.71V to 3.6V supply, allowing logic
inputs with a nominal swing of V
CCIN . If no power is
applied to V CCIN when power is applied to V CC , the
inputs are disabled and PWRDWN is internally driven
low, putting the device in the power-down state.
Power-Supply Circuits and Bypassing
The MAX9217 has isolated on-chip power domains. The
digital core supply (V
CC ) and single-ended input supply
(V
CCIN
) are isolated but have a common ground (GND).
The PLL has separate power and ground (V CCPLL and
V CCPLL GND) and the LVDS input also has separate
power and ground (V CCLVDS and V CCLVDS GND). The
grounds are isolated by diode connections. Bypass each
V
CC , V CCIN , V CCPLL , and V CCLVDS pin with high-frequen-
cy, surface-mount ceramic 0.1µF and 0.001µF capacitors
in parallel as close to the device as possible, with the
smallest value capacitor closest to the supply pin.
LVDS Output
The LVDS output is a current source. The voltage swing
is proportional to the termination resistance. The output
is rated for a differential load of 100
Ω ±1%.
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100
Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.