Table 1. offset dac codes, Table 2. serial data format – Rainbow Electronics MAX5735 User Manual
Page 17
MAX5732–MAX5735
32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
______________________________________________________________________________________
17
it is the offset DAC that determines the end-point volt-
ages of the range. Table 1 shows the offset DAC code
required during power-up.
Note: The offset DAC of every device can be pro-
grammed with any of the four output voltage ranges.
However, the specifications in the Electrical
Characteristics table are only guaranteed (production
tested) for the offset code associated with each partic-
ular part number. For example, the MAX5734 specifica-
tions are only valid with the MAX5734 offset- DAC code
shown in Table 1.
The offset DAC is summed with GS (Figure 1). The offset
DAC can also cancel the offset of the output buffers.
Any change in the offset DAC affects all 32 DACs.
The offset DAC is also configured identically to the
other 32 DACs with an input and DAC register. Write to
the offset DAC through the serial interface by using
control bits C2, C1, and C0 = 001 followed by the data
bits D15–D0. The
CLR command affects the offset DAC
as well as the other DACs.
The data format for the offset DAC codes are: control bits
C2, C1, and C0 = 011, address bits A5–A0 = 100000, 7
don’t-care bits, and 16 data bits as shown in Table 2.
Output Amplifiers (OUT0–OUT31)
All DAC outputs are internally buffered. The internal
buffers provide gain, improved load regulation, and tran-
sition glitch suppression for the DAC outputs. The output
buffers slew at 1V/µs and can drive 10k
Ω in parallel with
100pF. The output buffers are powered by AV
CC
and
V
SS
. AV
CC
and V
SS
determine the maximum output
voltage range of the device.
The input code, the voltage reference, the offset DAC
output, the voltage on GS, and the gain of the output
amplifier determine the output voltage. Calculate V
OUT
as follows:
where GAIN = 5/3 for the MAX5732, or GAIN = 10/3 for
the MAX5733/MAX5734/MAX5735.
Load-DAC (
LDAC) Input
The MAX5732–MAX5735 feature an active-low
LDAC
logic input that allows the outputs OUT_ to update
asynchronously. Keep
LDAC high during normal opera-
tion (when the device is controlled only through the ser-
ial interface). Drive
LDAC low to simultaneously update
all DAC outputs with data from their respective input
registers. Figure 3 shows the
LDAC timing with respect
to OUT_.
V
GAIN
V
DAC code
offset DAC code
V
OUT
REF
GS
=
Ч
Ч
(
)
+
−
2
16
PART NUMBER
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MAX5732
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MAX5733
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MAX5734
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MAX5735
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 1. Offset DAC Codes
OUT_
±0.5 LSB
t
S
t
LDAC
LDAC
Figure 3.
LDAC Timing
Note: For the MAX5732, the maximum code for the offset DAC is 16384. For the MAX5733/MAX5734/MAX5735, the maximum code
for the offset DAC is 40000.
Table 2. Serial Data Format
CONTROL
BITS
ADDRESS
BITS
DON’T-
CARE
BITS
DATA BITS
C2, C1,
AND C0
A5–A0
—
D15–D0
011
100000
XXXXXXX
See table 1