C&H Technology 82RIA...PbF Series - Manual (Page 3)

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2 [email protected] , [email protected] , [email protected] Revision: 17-Sep-10
80RIA...PbF, 81RIA...PbF, 82RIA...PbF Series
Vishay Semiconductors Phase Control Thyristors
(Stud Version), 80 A
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum average on-state current
at case temperature
I
T(AV)
180° conduction, half sine wave
80 A
85 °C
Maximum RMS on-state current I
T(RMS)
DC at 75 °C case temperature 125
A Maximum peak, one-cycle
non-repetitive surge current
I
TSM
t = 10 ms No voltage
reapplied
Sinusoidal half wave,
initial T
J
= T
J
maximum
1900
t = 8.3 ms 1990
t = 10 ms 100 % V
RRM
reapplied
1600
t = 8.3 ms 1675
Maximum I 2 t for fusing I 2 t
t = 10 ms
No voltage
18
kA 2 s
t = 8.3 ms 16
t = 10 ms 100 % V
RRM
reapplied
12.7
t = 8.3 ms 11.7
Maximum I 2 t for fusing I 2 t t = 0.1 ms to 10 ms, no voltage reapplied 180.5 kA 2 s
Low level value of threshold voltage V
T(TO)1
(16.7 % x
 x I
T(AV)
< I <
 x I
T(AV)
), T
J
= T
J
maximum 0.99
V
High level value of threshold voltage V
T(TO)2
(I >
 x I
T(AV)
), T
J
= T
J
maximum 1.13
Low level value of on-state slope resistance r
t1
(16.7 % x
 x I
T(AV)
< I <
 x I
T(AV)
), T
J
= T
J
maximum 2.29
m

High level value of on-state slope resistance r
t2
(I >
 x I
T(AV)
), T
J
= T
J
maximum 1.84
Maximum on-state voltage V
TM
I
pk
= 250 A, T
J
= 25 °C, t
p
= 10 ms sine pulse 1.60 V
Maximum holding current I
H
T
J
= 25 °C, anode supply 12 V resistive load
200
mA
Typical latching current I
L
400
SWITCHING
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum non-repetitive rate of
rise of turned-on current
dI/dt
T
J
= 125 °C, V
d
= Rated V
DRM
, I
TM
= 2 x dI/dt snubber
0.2 μF, 15 , gate pulse: 20 V, 65 , t
p
= 6 μs, t
r
= 0.5 μs
Per JEDEC standard RS-397, 5.2.2.6.
300 A/μs
Typical delay time t
d
Gate pulse: 10 V, 15
 source, t
p
= 6 μs, t
r
= 0.1 μs,
V
d
= Rated V
DRM
, I
TM
= 50 Adc, T
J
= 25 °C
1
μs
Typical turn-off time t
q
I
TM
= 50 A, T
J
= T
J
maximum, dI/dt = - 5 A/μs, V
R
= 50 V,
dV/dt = 20 V/μs, gate bias: 0 V 25
, t
p
= 500 μs
110
BLOCKING
PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS
Maximum critical rate of rise of
off-state voltage
dV/dt T
J
= 125 °C exponential to 67 % rated V
DRM
500 V/μs
Maximum peak reverse and
off-state leakage current I
RRM
,
I
DRM
T
J
= 125 °C rated V
DRM
/V
RRM
applied 15 mA