Xilinx ML605 - Manual (Page 32)

32 www.xilinx.com ML605 Hardware User Guide
UG534 (v1.8) October 2, 2012
Chapter 1: ML605 Evaluation Board
GTX SMA Clock
The ML605 includes a pair of SMA connectors for a GTX (MGT) Clock as described in
Figure 1-9 and Table 1-7 .
X-Ref Target - Figure 1-9
Figure 1-9: GTX SMA Clock
UG534_09_081309
SMA_REFCLK_C_N1
J30 32K10K-400E3
J31 32K10K-400E3
SMA_REFCLK_N
SMA_REFCLK_P
SMA_REFCLK_C_P1
GND1
GND2
GND3
GND4
SIG
SIG
GND5
GND6
GND7
GND1
GND2
GND3
GND4
GND5
GND6
GND7
2
3
4
5
6
7
8
2
3
4
5
6
7
8
C61 1 0.1UF 10V X5R
2
C62 1 0.1UF 10V X5R
2
Table 1-7: ML605 Clock Connections
U1 FPGA Pin Schematic Net Name SMA Pin
H9 SYSCLK_N U11.5
J9 SYSCLK_P U11.4
U23 USER_CLOCK X5.5
F5 SMA_REFCLK_N J30.1
F6 SMA_REFCLK_P J31.1
M22 USER_SMA_CLOCK_N J55.1
L23 USER_SMA_CLOCK_P J58.1