Xilinx ML605 - Manual (Page 2)

ML605 Hardware User Guide www.xilinx.com UG534 (v1.8) October 2, 2012
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Revision History
The following table shows the revision history for this document.
Date Version Revision
8/17/09 1.0 Initial Xilinx release.
11/17/09 1.1 • Updated Figure 1-1 , Figure 1-2 , Figure 1-3 , Figure 1-11 , and Figure 1-14 .
• Added Figure 1-7 , Figure 1-8 , Figure 1-10 , and Figure 1-13 .
• Updated Table 1-15 and Table 1-18 .
• Updated Appendix C, VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout and
Appendix D, ML605 Master UCF .
• Minor typographical edits.
01/15/10 1.2 • Updated Figure 1-2 , Figure 1-3 , Figure 1-17 , Table 1-3 , Table 1-8 , Table 1-9 , Table B-34 ,
and Table B-35 . Miscellaneous typographical edits.
1/21/10 1.2.1 • Corrected typos in Table 1-31 and Figure 1-28 .
05/18/10 1.3 Updated 7. Clock Generation , including Table 1-7 . Updated Package Placement column
in Table 1-8 . Updated Figure 1-17 . Added notes about FMC HPC J64 and J63 connectors
to 19. VITA 57.1 FMC HPC Connector and 20. VITA 57.1 FMC LPC Connector ,
respectively. Updated description of PMBus Pod and TI Fusion Digital Power Software
GUI in
Onboard Power Regulation . Updated Table B-35 , Appendix C, VITA 57.1 FMC
LPC (J63) and HPC (J64) Connector Pinout , and Appendix D, ML605 Master UCF .
10/12/10 1.4 Updated description of Fusion Digital Power Software in Onboard Power Regulation .
02/15/11 1.5 Revised note in Table 1-6 . Revised oscillator manufacturer information from Epson to
SiTime on page page 14 , page 29 and page 78 .
07/18/11 1.6 Corrected “jitter” to “stability” in section Oscillator (Differential), page 29 . Added
Table 1-32, page 69 , and table notes in Table 1-31 . Revised the FPGA U1 Pins for
IIC_SDA_MAIN and IIC_SCL_MAIN in Table 1-18, page 46 .