Xilinx ChipScope PLB46 IBA v1.00a - Manual (Page 4)

4 www.xilinx.com DS619 April 7, 2009
Product Specification
P54 MU_9 Sl_MWrErr[0:
C_PLBV46_NUM_SLAVES
*C_PLBV46_NUM_MASTERS-1]
Slave I Slave write error indicator
PLB Arbitration Signals
P55 MU_10 M_request[0:
C_PLBV46_NUM_MASTERS-1] Master I Master bus request
P56 MU_10 M_priority[0:
C_PLBV46_NUM_MASTERS*2-1]
Master I Master bus request priority
P57 MU_10 M_busLock[0:
C_PLBV46_NUM_MASTERS-1] Master I Master Bus Lock
P58 MU_10 M_abort[0:
C_PLBV46_NUM_MASTERS-1] Master I Master abort bus request indicator
P59 MU_10 PLB_rdPendPri[0:1] Master I PLB pending read request priority
P60 MU_10 PLB_wrPendPri[0:1] Master I PLB pending write request priority
P61 MU_10 PLB_rdPendReq Master /
Slave I PLB pending bus read request indicator
P62 MU_10 PLB_wrPendReq Master /
Slave I PLB pending bus write request indicator
P63 MU_10 PLB_reqPri[0:1] Master /
Slave
I PLB current request priority
PLB Master Signals
P64 MU_11 M_lockErr[0:
C_PLBV46_NUM_MASTERS-1] Master I Master lock error indicator
P65 MU_11 M_rdBurst[0:
C_PLBV46_NUM_MASTERS-1]
Master I Master read burst indicator
P66 MU_11 M_wrBurst[0:
C_PLBV46_NUM_MASTERS-1] Master I Master write burst indicator
P67 MU_11 M_RNW[0:
C_PLBV46_NUM_MASTERS-1] Master I Master read not write
P68 MU_11 PLB_MBusy[0:
C_PLBV46_NUM_MASTERS-1]
Master I PLB Master slave busy indicator
P69 MU_11 PLB_MAddrAck[0:
C_PLBV46_NUM_MASTERS-1] Master I PLB Master Address acknowledge
P70 MU_11 PLB_MRdBTerm[0:
C_PLBV46_NUM_MASTERS-1] Master I PLB Master terminate read burst indicator
P71 MU_11 PLB_MRdDAck[0:
C_PLBV46_NUM_MASTERS-1]
Master I PLB Master read data acknowledge
P72 MU_11 PLB_MRearbitrate[0:
C_PLBV46_NUM_MASTERS-1] Master I PLB Master bus re-arbitrate indicator
P73 MU_11 PLB_MWrBTerm[0:
C_PLBV46_NUM_MASTERS-1] Master I PLB Master terminate write burst
indicator
P74 MU_11 PLB_MWrDAck[0:
C_PLBV46_NUM_MASTERS-1] Master I PLB Master write data acknowledge
P75 MU_12 M_mSize[0:
C_PLBV46_NUM_MASTERS*2-1] Master I Master data bus port width
Table 1: IBA_PLBv46 Pin Descriptions (Cont’d)
Port MU Signal Name Interface I/O Description