Xilinx ChipScope PLB46 IBA v1.00a - Manual (Page 12)

12 www.xilinx.com DS619 April 7, 2009
Product Specification
Design Implementation
The ChipScope PLB IBA design is implemented in a Tcl script. When the EDK Platgen tool is run, this Tcl script
is called and it internally calls the ChipScope Pro Core generator in command line mode providing a generated
argument (.arg) file to create a customized ILA. This ILA is customized per the IBA settings and is attached to the
PLB46 bus using a custom HDL wrapper.
XST is the synthesis tool used for synthesizing the wrapper HDL generated for the ChipScope PLB IBA. The
EDIF netlist output from XST and ChipScope Core Generator are then input to the Xilinx Foundation tool suite
for actual device implementation.
Target Technology
The intended target technology is all Xilinx FPGAs.
Device Utilization and Performance Benchmarks
The device utilization varies widely based on the parameter combinations set by the user.
Restrictions
Maximum number of signals that can be stored for non-Virtex-5 device families is limited to 256 signals. For Vir-
tex-5 family devices the limit is 1024 signals.
References
• More information on the ChipScope Pro software and cores is available in the Software and Cores User
Guide, located at
http://www.xilinx.com/documentation .
• Information about hardware debugging using ChipScope Pro in EDK is available in the Platform Studdio
11.1 online help, located at
http://www.xilinx.com/documentation .
• Information about hardware debugging using ChipScope Pro in System Generator for DSP is available in
the Xilinx System Generator for DSP User Guide, located at
http://www.xilinx.com/documentation .
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product documenta-
tion. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that are not
defined in the documentation, if customized beyond that allowed in the product documentation, or if changes are
made to any section of the design labeled DO NOT MODIFY.
Ordering Information
The PLB IBA core is provided under the ISE Design Suite End-User License Agreement and can be generated
using the Xilinx Embedded Development Kit (EDK) system 11.1 or higher. EDK is shipped with the Xilinx ISE
Design Suite development software.