Texas Instruments 51X - Manual (Page 43)

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Integral address decoder - provides selection of all primary and
secondary ISA addresses including COM1-4 and LPT1-3.
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Enhanced Power Management Function
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Special configuration registers for power down
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Enhanced programmable power-down and wake-up modes
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Auto power-down and wake-up modes
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3 special pins for power management
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Typical current consumption during power-down is less than 10A
4.2.3
Video Subsystem
The video subsystem, implemented on the Main Board and on the LCD
Display Unit, displays text, graphics and drives an external VGA port. The
video subsystem is implemented with a Chips and Technology high
performance flat panel/RT VGA controller and supporting logic and video
RAM (1 MB).
The major features of the VGA controller include:
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Highly integrated design (flat panel / CRT VGA controller, RAMDAC,
clock synthesizer)
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Multiple Bus Architecture Integrated Interface
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Local Bus (32-bit CPU Direct and VL)
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PCI Bus
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EISA/ISA (PC/AT) 16-bit Bus
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Advanced frame buffer architecture uses available display memory,
maximizing integration and minimizing chip count
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Integrated programmable linear address feature accelerates GUI
performance
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High performance resulting from zero wait state writes (write buffer) and
minimum wait state reads (internal asynchronous FIFO design)
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Supports panel resolutions up to 800 x 600
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SMARTMAP intelligent color to gray scale conversion enhances text
legibility
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Text enhancement feature improves white text contrast on flat panel
displays
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Fully Compatible with IBM VGA
4-4 Theory of Operation