Texas Instruments TMS320C6455 - Manual (Page 44)

DDR2 Memory Controller Registers www.ti.com
4.5 SDRAM Timing 1 Register (SDTIM1)
The SDRAM timing 1 register (SDTIM1) configures the DDR2 memory controller to meet many of the AC
timing specification of the DDR2 memory. Note that DDR2CLKOUT is equal to the period of the
DDR2CLKOUT signal. For information on the appropriate values to program each field, see the DDR2
memory section of the device-specific data manual. The bit fields in the SDTIM1 register are only
writeable when the TIMUNLOCK bit of the SDRAM Configuration register (SDCFG) is unlocked. The
SDTIM1 is shown in
Figure 23 and described in Table 22 .
Figure 23. SDRAM Timing 1 Register (SDTIM1)
31 25 24 22 21 19 18 16
T_RFC T_RP T_RCD T_WR
R/W-0x3F R/W-0x7 R/W-0x7 R/W-0x7
15 11 10 6 5 3 2 1 0
T_RAS T_RC T_RRD Rsvd T_WTR
R/W-0x1F R/W-0x1F R/W-0x7 R-0 R/W-0x3
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions
Bit Field Value Description
31-25 T_RFC These bits specify the minimum number of DDR2CLKOUT cycles from a refresh or load mode
command to a refresh or activate command, minus one. The value for these bits can be derived
from the t
rfc
AC timing parameter in the DDR2 memory section of the device-specific data manual.
Calculate using this formula:
T_RFC = (t
rfc
/DDR2CLKOUT) - 1
24-22 T_RP These bits specify the minimum number of DDR2CLKOUT cycles from a precharge command to a
refresh or activate command, minus 1. The value for these bits can be derived from the t
rp
AC
timing parameter in the DDR2 memory section of the device-specific data manual. Calculate using
the formula:
T_RP = (t
rp
/DDR2CLKOUT) - 1
21-19 T_RCD These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to a
read or write command, minus 1. The value for these bits can be derived from the t
rcd
AC timing
parameter in the DDR2 memory section of the device-specific data manual. Calculate using the
formula:
T_RCD = (t
rcd
/DDR2CLKOUT) - 1
18-16 T_WR These bits specify the minimum number of DDR2CLKOUT cycles from the last write transfer to a
precharge command, minus 1. The value for these bits can be derived from the t
wr
AC timing
parameter in the DDR2 memory section of the device-specific data manual. Calculate using the
formula:
T_WR = (t
wr
/DDR2CLKOUT) - 1
The SDRAM initialization sequence will be started when the value of this field is changed from the
previous value and the DDR2_ENABLE in SDCFG is equal to 1.
15-11 T_RAS These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to a
precharge command, minus 1. The value for these bits can be derived from the t
ras
AC timing
parameter in the DDR2 memory section of the device-specific data manual. Calculate using this
formula:
T_RAS = (t
ras
/DDR2CLKOUT) - 1
T_RAS must be greater than or equal to T_RCD.
10-6 T_RC These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to an
activate command, minus 1. The value for these bits can be derived from the t
rc
AC timing
parameter in the DDR2 memory section of the device-specific data manual. Calculate using this
formula:
T_RC = (t
rc
/DDR2CLKOUT) - 1
44 C6455/C6454 DDR2 Memory Controller SPRU970G – December 2005 – Revised June 2011
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