Table 15, Table 15. sdtim2 configuration – Texas Instruments TMS320C6455 User Manual
Page 37

Using the DDR2 Memory Controller
Table 15. SDTIM2 Configuration
DDR2 SDRAM Data
Register Field
Sheet Parameter
Data Sheet
Formula (Register
Field
Name
Name
Description
Value
Field Must Be
≥
)
Value
T_ODT
t
AOND
t
AOND
specifies the ODT turn-on
2 (t
CK
cycles)
t
AOND
2
delay
T_XSNR
t
XSNR
Exit self refresh to a non-read
137.5 ns
(t
XSNR
×
f
DDR2_CLK
) - 1
34
command
T_XSRD
t
XSRD
Exit self refresh to a read
200 (t
CK
cycles)
(t
XSRD
) - 1
199
command
T_RTP
t
RTP
Read to precharge command
7.5 ns
(t
RTP
×
f
DDR2_CLK
) - 1
1
delay
T_CKE
t
CKE
CKE minimum pulse width
3 (t
CK
cycles)
(t
CKE
) - 1
2
3.2.4
Configuring the DDR2 Memory Controller Control Register (DMCCTL)
The DDR2 memory controller control register (DMCCTL) contains a read latency (RL) field that helps the
DDR2 memory controller determine when to sample read data. The RL field should be programmed to a
value equal to CAS latency + 1. For example, if a CAS latency of 4 is used, then RL should be
programmed to 5.
Table 16. DMCCTL Configuration
Register
Register Field Name
Description
Value
IFRESET
Programmed to be out of reset.
0
RL
Read latency is equal to CAS latency + 1.
5
37
SPRU970G
–
December 2005
–
Revised June 2011
C6455/C6454 DDR2 Memory Controller
Copyright
©
2005
–
2011, Texas Instruments Incorporated