Renesas SuperH HS7710KCM02HE - Manual (Page 21)

15
8. Cache Operation during User Program Break
When cache is enabled, the emulator accesses the memory by the following methods:

At memory write: Writes through the cache, then writes to the memory.

At memory read: Does not change the cache write mode that has been set.
Therefore, when memory read or write is performed during user program break, the cache state
will be changed.
9. UBC
When [User] is specified in the [UBC mode] list box in the [Configuration] dialog box, the
UBC can be used in the user program.
Do not use the UBC in the user program as it is used by the emulator when [EML] is specified
in the [UBC mode] list box in the [Configuration] dialog box.
10. Memory Access during Break
In the enabled MMU, when a memory is accessed and a TLB error occurs during break, it can
be selected whether the TLB exception is controlled or the program jumps to the user
exception handler in [TLB Mode] in the [Configuration] dialog box. When [TLB miss
exception is enable] is selected, a Communication Timeout error will occur if the TLB
exception handler does not operate correctly. When [TLB miss exception is disable] is
selected, the program does not jump to the TLB exception handler even if a TLB exception
occurs. Therefore, if the TLB exception handler does not operate correctly, a Communication
Timeout error will not occur but the memory contents may not be correctly displayed.
11. Loading Sessions
Information in [JTAG clock] of the [Configuration] dialog box cannot be recovered by loading
sessions. Thus the TCK value will be as follows:

When HS7710KCI01H or HS7710KCI02H is used: TCK = 4.125 MHz

When HS7710KCM01H or HS7710KCM02H is used: TCK = 3.75 MHz
12. [IO] Window

Display and modification
Do not change values of the User Break Controller because it is used by the emulator.
For each watchdog timer register, there are two registers to be separately used for write and
read operations.