Renesas Emulation Pod M3062NT3-RPD-E User Manual

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(2) Separate Bus, With Wait, Accessing External Memory Area

Table 5.3 and Figure 5.2 show the bus timing in memory expansion and microprocessor modes (with
wait, accessing external area).

Table 5.3 Memory expansion and microprocessor modes (with wait, accessing external area)

*1 Calculated by the following formula according to the frequency of BCLK.

td(DB-WR)=

-50 [ns]

f(BCLK)

Symbol

Item

Actual MCU

[ns]

This product

[ns]

Min.

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

th(WR-AD)

td(BCLK-CS)

th(BCLK-CS)

td(BCLK-ALE)

th(BCLK-ALE)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

th(WR-DB)

Min.

Max.

Address output delay time

Address output hold time (BCLK standard)

Address output hold time (RD standard)

Address output hold time (WR standard)

Chip-select output delay time

Chip-select output hold time (BCLK standard)

ALE signal output delay time

ALE signal output hold time

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

Data output delay time (BCLK standard)

Data output hold time (BCLK standard)

Data output delay time (WR standard)

Data output hold time (WR standard)

-4

(*1)

See left

-4

See left

Max.

See left