Renesas SH7201 - Manual (Page 24)

JA3
Pin Header Name CPU board
Signal Name
Device Pin Pin Header Name CPU board
Signal Name
Device Pin
1 BA(0) BA(0) - 26 BWRn BWRn -
2 BA(1) BA(1) - 27 BCS1n BCS1n -
3 BA(2) BA(2) - 28 BCS2n BCS2n -
4 BA(3) BA(3) - 29 BD(8) BD(8) -
5 BA(4) BA(4) - 30 BD(9) BD(9) -
6 BA(5) BA(5) - 31 BD(10) BD(10) -
7 BA(6) BA(6) - 32 BD(11) BD(11) -
8 BA(7) BA(7) - 33 BD(12) BD(12) -
9 BA(8) BA(8) - 34 BD(13) BD(13) -
10 BA(9) BA(9) - 35 BD(14) BD(14) -
11 BA(10) BA(10) - 36 BD(15) BD(15) -
12 BA(11) BA(11) - 37 BD(16) BD(16) -
13 BA(12) BA(12) - 38 BD(17) BD(17) -
14 BA(13) BA(13) - 39 BD(18) BD(18) -
15 BA(14) BA(14) - 40 BD(19) BD(19) -
16 BA(15) BA(15) - 41 BD(20) BD(20) -
17 BD(0) BD(0) - 42 BD(21) BD(21) -
18 BD(1) BD(1) - 43 BD(22) BD(22) -
19 BD(2) BD(2) - 44 BSDCLK BSDCLK -
20 BD(3) BD(3) - 45 BCS3n BCS3n -
21 BD(4) BD(4) - 46 Bus Control --- -
22 BD(5) BD(5) - 47 BWR1n BWR1n -
23 BD(6) BD(6) - 48 BWR0n BWR0n -
24 BD(7) BD(7) - 49 Data Bus Strobe --- -
25 BRDn BRDn - 50 Reserved --- -
Table 8-7: JA3 Standard Generic Header
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