Nvidia TEGRA DG-04927-001_V01 - Manual (Page 20)

Tegra 200 Series Developer Board User Guide
DG-04927-001_v01 Advance Information – Subject to Change 20
NVIDIA CONFIDENTIAL
4.2 Clocks
The Tegra 250 has a large number of internal functional blocks supporting a broad range of interfaces. Each of these has its
own clocking requirements. The RTC (Real Time Clock) and PMC (Power Management Controller) require a 32.768KHz clock,
to be provided externally. In addition, a higher frequency reference clock (OSC) is required. This can come from a crystal or an
external source, and feeds several integrated PLLs that provide a variety of clocking options for the core and I/O blocks. The
Tegra 250 clocking scheme is shown in Figure 8.
Figure 8. Tegra 250 Clocking Block Diagram
4.2.1 32.768KHz Clock
The 32.768KHz clock is provided externally by the PMU. This clock is input on the CLK_32K_IN pin which is referenced to the
VDDIO_SYS rail. See the Tegra 200 Series Datasheet (Electrical, Mechanical and Thermal Specifications) for details on the
requirements for this clock.
4.2.2 Oscillator Clock
The Tegra 200 Series Developer Board utilizes a 12MHz crystal connected to the Tegra 250 XTAL_IN, XTAL_OUT pins to
generate the reference clock internally. A reference circuit is shown in Figure 9.
Table 6 contains the requirements for the crystal used, the value of the parallel bias resistor and information to calculate the
values of the two external load capacitors (C
L1
and C
L2
) shown in the circuit.