National Instruments VXI-MIO Series User Manual
Vxi-mio series user manual
Table of contents
Document Outline
- VXI-MIO Series User Manual
- Important Information
- Chapter 1 Introduction
- Chapter 2 Configuration and Installation
- Chapter 3 Hardware Overview
- Chapter 4 Signal Connections
- I/O Connector
- Analog Input Signal Connections
- Types of Signal Sources
- Input Configurations
- Analog Output Signal Connections
- Digital I/O Signal Connections
- Power Connections
- Timing Connections
- Field Wiring Considerations
- Chapter 5 Calibration
- Appendix A Specifications
- Appendix B Optional Cable Connector Descriptions
- Appendix C Common Questions
- Appendix D Customer Communication
- Glossary
- Index
- Figures
- Figure 1-1. The Relationship between the Programming Environment, Your Instrument Driver, and Your VXI-DAQ Hardware
- Figure 2-1. VXI-MIO-64E-1 Parts Locator Diagram
- Figure 2-2. VXI-MIO-64XE-10 Block Diagram
- Figure 2-3. VXI-MIO-64XE-10 Logical Address Selection
- Figure 2-4. SIMM Size Configuration
- Figure 2-5. Load User/Factory Configuration
- Figure 2-6. Protect/Change Factory Configuration
- Figure 3-1. VXI-MIO Series Block Diagram
- Figure 3-2. Dither
- Figure 3-3. Analog Trigger Block Diagram
- Figure 3-4. Below-Low-Level Analog Triggering Mode
- Figure 3-5. Above-High-Level Analog Triggering Mode
- Figure 3-6. Inside-Region Analog Triggering Mode
- Figure 3-7. High-Hysteresis Analog Triggering Mode
- Figure 3-8. Low-Hysteresis Analog Triggering Mode
- Figure 3-9. CONVERT* Signal Routing
- Figure 3-10. VXIbus Trigger Utilization
- Figure 4-1. I/O Connector Pin Assignment for the VXI-MIO-64E-1 and VXI-MIO-64XE-10
- Figure 4-2. VXI-MIO Series PGIA
- Figure 4-3. Summary of Analog Input Connections
- Figure 4-4. Differential Input Connections for Ground-Referenced Signals
- Figure 4-5. Differential Input Connections for Nonreferenced Signals
- Figure 4-6. Single-Ended Input Connections for Nonreferenced or Floating Signals
- Figure 4-7. Single-Ended Input Connections for Ground-Referenced Signal
- Figure 4-8. Analog Output Connections
- Figure 4-9. Digital I/O Connections
- Figure 4-10. Timing I/O Connections
- Figure 4-11. Typical Posttriggered Acquisition
- Figure 4-12. Typical Pretriggered Acquisition
- Figure 4-13. SCANCLK Signal Timing
- Figure 4-14. EXTSTROBE* Signal Timing
- Figure 4-15. TRIG1 Input Signal Timing
- Figure 4-16. TRIG1 Output Signal Timing
- Figure 4-17. TRIG2 Input Signal Timing
- Figure 4-18. TRIG2 Output Signal Timing
- Figure 4-19. STARTSCAN Input Signal Timing
- Figure 4-20. STARTSCAN Output Signal Timing
- Figure 4-21. CONVERT* Input Signal Timing
- Figure 4-22. CONVERT* Output Signal Timing
- Figure 4-23. SISOURCE Signal Timing
- Figure 4-24. WFTRIG Input Signal Timing
- Figure 4-25. WFTRIG Output Signal Timing
- Figure 4-26. UPDATE* Input Signal Timing
- Figure 4-27. UPDATE* Output Signal Timing
- Figure 4-28. UISOURCE Signal Timing
- Figure 4-29. GPCTR0_SOURCE Signal Timing
- Figure 4-30. GPCTR0_GATE Signal Timing in Edge-Detection Mode
- Figure 4-31. GPCTR0_OUT Signal Timing
- Figure 4-32. GPCTR1_SOURCE Signal Timing
- Figure 4-33. GPCTR1_GATE Signal Timing in Edge-Detection Mode
- Figure 4-34. GPCTR1_OUT Signal Timing
- Figure 4-35. GPCTR Timing Summary
- Figure B-1. 68-Pin MIO Connector Pin Assignments
- Figure B-2. 68-Pin Extended Analog Input Connector Pin Assignments
- Tables
- Table 2-1. VXI-MIO Series DRAM Configuration
- Table 3-1. Available Input Configurations for the VXI-MIO Series
- Table 3-2. Actual Range and Measurement Precision
- Table 3-3. Actual Range and Measurement Precision, VXI-MIO-64XE-10
- Table 4-1. VXI-MIO-64E-1 I/O Signal Summary
- Table 4-2. VXI-MIO-64XE-10 I/O Signal Summary