5 equalizer settings, Section 9.5.5, Tfa9812 – NXP Semiconductors TFA9812 User Manual
Page 33: Nxp semiconductors
TFA9812_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 22 January 2009
33 of 66
NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplifier with I
2
S input
9.5.5 Equalizer settings
[1]
Default settings are shown in
. The corresponding equalizer configuration is shown in
.
[1]
Default settings are shown in
. The corresponding equalizer configuration is shown in
.
Table 35.
Bit description of register 03h: equalizer configuration
Bit
Symbol
Description
1
EQ_BP
Equalizer bypass enable:
0 = Equalizer not bypassed
1 = Equalizer bypassed
0
EQ_BND
Equalizer 10-band or 5-band configuration selection:
0 = 10-band equalizer configuration enabled
1 = 5-band equalizer configuration enabled
Table 36.
Register addresses xxh = 04, 06...2A
For word1 for equalizer 'yy' see
Bit
15
14
13
12
11
10
9
8
Symbol
Eyy_t
1
Eyy_k
1m
10
Eyy_k
1m
9
Eyy_k
1m
8
Eyy_k
1m
7
Eyy_k
1m
6
Eyy_k
1m
5
Eyy_k
1m
4
Default
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
Symbol
Eyy_k
1m
3
Eyy_k
1m
2
Eyy_k
1m
1
Eyy_k
1m
0
Eyy_k
1e
3
Eyy_k
1e
2
Eyy_k
1e
1
Eyy_k
1e
0
Default
-
-
-
-
-
-
-
-
Table 37.
Register addresses xxh = 05, 07...2B
For word2 for equalizer 'yy' see
Bit
15
14
13
12
11
10
9
8
Symbol
Eyy_t
2
Eyy_k
2m
3
Eyy_k
2m
2
Eyy_k
2m
1
Eyy_k
2m
0
Eyy_k
2e
2
Eyy_k
2e
1
Eyy_k
2e
0
Default
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
Symbol
Eyy_k
0
6
Eyy_k
0
5
Eyy_k
0
4
Eyy_k
0
3
Eyy_k
0
2
Eyy_k
0
1
Eyy_k
0
0
Eyy_s
Default
-
-
-
-
-
-
-
-