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8 board reset scheme, Table 14. reset requirements/schemes, Figure 10. reset sources – Intel IQ80333 User Manual

Page 37: Ddr ii sdram, Pci-x con a pci-x con b jtag con, Pci-e con

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Customer Reference Board Manual

37

Intel® IQ80333 I/O Processor

Hardware Reference Section

3.8

Board Reset Scheme

Figure 10

depicts the reset scheme for the 80333.

Table 14

list the reset schemes for the 80333.

Table 14.

Reset Requirements/Schemes

Description

Primary PCI reset, resets all devices on the board. It occurs during the power-up.

The SRST signal from the JTAG connector is a bi-directional signal that can force a reset similar to the
power-up reset on the board.

Figure 10.

RESET Sources

DDR II SDRAM

Intel® 80333 I/O

Processor

PCI-X Con A

PCI-X Con B

JTAG

Con

Debounce

CPLD

A_RST#

B_RST#

RST#

LAN_PWR_GOOD

PWRGD

TRST
#

SRST
#

Power

Delay

RESETIN
#

Reset

Button

82545EM

TRST
#

M_RST#

PWRDELAY

PCI-E Con

Pwrgood

Isolation

Voltage
Monitor