Intel Xeon - Manual (Page 26)

26 Intel ® Xeon™ Processor, Intel ® E7520 Chipset, Intel ® 6300ESB ICH Development Kit User’s Manual
System Overview
5.2 Platform Clocking
The CRB uses one CK409B Clock Synthesizer to generate the host differential pair clocks and the
100 MHz differential clock to the DB800. The DB800 then generates the 100 MHz differential pair
clock for the PCI Express* devices.
Figure 6 shows the CRB clock configuration.
Figure 6. Clock Block Diagram
B2937-03
Intel
®
6300ESB
I/O
Controller
Hub
MCH
CPU0_BCLK
CPU1_BCLK
DDRA
CPU0
CPU1
ITP_BCLK
DDRA_CMDCLK[1:0] ITP
MCH_BCLK
DDRB
DDRB_CMDCLK[1:0]
ICH_PX_PCLK0[1:0]
MCH_66MHZ_CLK
32.786 MHz
ICH_SUSCLK
ICH_SRC_100MHZ_CLK
MCH_SRC_100MHZ_CLK
PXH_PBPCLKO[0..1]
PXH_PAPCLKO
SIO
SIO_33MHZ_CLK
VIDEO_33MHZ_CLK
LPC_14MHZ_CLK
HI LAI
PXH
LAI_H166MHZ_CLK
DB800_SRC_100MHZ_CLK
PXH_SRC_
100MHZ_CLK
ICH_USB_48MHZ_CLK
LPZ_14MHZ_CLK
ICH_H166MHZ_CLK
ICH_33MHZ_CLK
ICH_PX66MHZ_CLK
29.499 MHz
Video
FWH_33MHZ_CLK
FWH
PORT80_33MHZ_CLK
Port 80
EXP_SLOT5_
100MHZ_CLK
EXP_SLOT6_
100MHZ_CLK
PCI Express Slot
PCI Express Slot
PCI_SLOT6_33MHZ_CLK
PCI 2.2
DB800
PCI-X
PCI-X
PCI-X
CK-409
14.318
MHz
SMA